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add support for pentium class CPUs which do not have cmov,
PR4841. Patch by Craig Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98496 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -8478,6 +8478,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::CMOV_V4F32:
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case X86::CMOV_V2F64:
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case X86::CMOV_V2I64:
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case X86::CMOV_GR16:
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case X86::CMOV_GR32:
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case X86::CMOV_RFP32:
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case X86::CMOV_RFP64:
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case X86::CMOV_RFP80:
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return EmitLoweredSelect(MI, BB, EM);
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case X86::FP32_TO_INT16_IN_MEM:
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@ -350,20 +350,27 @@ def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">;
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def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">;
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// Floating point cmovs.
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class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
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class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
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multiclass FPCMov<PatLeaf cc> {
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def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
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def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
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CondMovFP,
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[(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
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cc, EFLAGS))]>;
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def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
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def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
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CondMovFP,
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[(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
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cc, EFLAGS))]>;
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def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
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CondMovFP,
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[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
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cc, EFLAGS))]>;
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cc, EFLAGS))]>,
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Requires<[HasCMov]>;
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}
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let Uses = [EFLAGS], isTwoAddress = 1 in {
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defm CMOVB : FPCMov<X86_COND_B>;
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defm CMOVBE : FPCMov<X86_COND_BE>;
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@ -375,6 +382,7 @@ defm CMOVNE : FPCMov<X86_COND_NE>;
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defm CMOVNP : FPCMov<X86_COND_NP>;
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}
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let Predicates = [HasCMov] in {
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// These are not factored because there's no clean way to pass DA/DB.
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def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
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@ -392,6 +400,7 @@ def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
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def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
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} // Predicates = [HasCMov]
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// Floating point loads & stores.
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let canFoldAsLoad = 1 in {
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@ -297,6 +297,8 @@ def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
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//===----------------------------------------------------------------------===//
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// X86 Instruction Predicate Definitions.
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def HasCMov : Predicate<"Subtarget->hasCMov()">;
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def NoCMov : Predicate<"!Subtarget->hasCMov()">;
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def HasMMX : Predicate<"Subtarget->hasMMX()">;
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def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
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def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
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@ -1213,19 +1215,7 @@ let isTwoAddress = 1 in {
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// Conditional moves
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let Uses = [EFLAGS] in {
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// X86 doesn't have 8-bit conditional moves. Use a customInserter to
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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// however that requires promoting the operands, and can induce additional
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// i8 register pressure. Note that CMOV_GR8 is conservatively considered to
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// clobber EFLAGS, because if one of the operands is zero, the expansion
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// could involve an xor.
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let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
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def CMOV_GR8 : I<0, Pseudo,
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(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
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"#CMOV_GR8 PSEUDO!",
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[(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
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imm:$cond, EFLAGS))]>;
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let Predicates = [HasCMov] in {
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let isCommutable = 1 in {
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def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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@ -1613,6 +1603,49 @@ def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_NO, EFLAGS))]>,
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TB;
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} // Predicates = [HasCMov]
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// X86 doesn't have 8-bit conditional moves. Use a customInserter to
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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// however that requires promoting the operands, and can induce additional
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// i8 register pressure. Note that CMOV_GR8 is conservatively considered to
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// clobber EFLAGS, because if one of the operands is zero, the expansion
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// could involve an xor.
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let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
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def CMOV_GR8 : I<0, Pseudo,
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(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
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"#CMOV_GR8 PSEUDO!",
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[(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
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imm:$cond, EFLAGS))]>;
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let Predicates = [NoCMov] in {
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def CMOV_GR32 : I<0, Pseudo,
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
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"#CMOV_GR32* PSEUDO!",
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[(set GR32:$dst,
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(X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
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def CMOV_GR16 : I<0, Pseudo,
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
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"#CMOV_GR16* PSEUDO!",
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[(set GR16:$dst,
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(X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
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def CMOV_RFP32 : I<0, Pseudo,
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(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
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"#CMOV_RFP32 PSEUDO!",
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[(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
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EFLAGS))]>;
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def CMOV_RFP64 : I<0, Pseudo,
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(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
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"#CMOV_RFP64 PSEUDO!",
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[(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
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EFLAGS))]>;
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def CMOV_RFP80 : I<0, Pseudo,
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(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
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"#CMOV_RFP80 PSEUDO!",
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[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
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EFLAGS))]>;
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} // Predicates = [NoCMov]
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} // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
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} // Uses = [EFLAGS]
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@ -133,6 +133,7 @@ public:
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PICStyles::Style getPICStyle() const { return PICStyle; }
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void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
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bool hasCMov() const { return HasCMov; }
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bool hasMMX() const { return X86SSELevel >= MMX; }
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bool hasSSE1() const { return X86SSELevel >= SSE1; }
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bool hasSSE2() const { return X86SSELevel >= SSE2; }
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