Rearrange some stuff in MachineOperand and add a new TargetFlags field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74087 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-06-24 17:54:48 +00:00
parent 8cbc94afb7
commit 31530617dd
2 changed files with 47 additions and 32 deletions

View File

@ -47,7 +47,14 @@ public:
private:
/// OpKind - Specify what kind of operand this is. This discriminates the
/// union.
MachineOperandType OpKind : 8;
unsigned char OpKind; // MachineOperandType
/// SubReg - Subregister number, only valid for MO_Register. A value of 0
/// indicates the MO_Register has no subReg.
unsigned char SubReg;
/// TargetFlags - This is a set of target-specific operand flags.
unsigned char TargetFlags;
/// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
/// operands.
@ -73,10 +80,6 @@ private:
/// model the GCC inline asm '&' constraint modifier.
bool IsEarlyClobber : 1;
/// SubReg - Subregister number, only valid for MO_Register. A value of 0
/// indicates the MO_Register has no subReg.
unsigned char SubReg;
/// ParentMI - This is the instruction that this operand is embedded into.
/// This is valid for all operand types, when the operand is in an instr.
MachineInstr *ParentMI;
@ -105,7 +108,9 @@ private:
} OffsetedInfo;
} Contents;
explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {}
explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {
TargetFlags = 0;
}
public:
MachineOperand(const MachineOperand &M) {
*this = M;
@ -115,7 +120,12 @@ public:
/// getType - Returns the MachineOperandType for this operand.
///
MachineOperandType getType() const { return OpKind; }
MachineOperandType getType() const { return (MachineOperandType)OpKind; }
unsigned char getTargetFlags() const { return TargetFlags; }
void setTargetFlags(unsigned char F) { TargetFlags = F; }
void addTargetFlag(unsigned char F) { TargetFlags |= F; }
/// getParent - Return the instruction that this operand belongs to.
///
@ -404,6 +414,7 @@ public:
SubReg = MO.SubReg;
ParentMI = MO.ParentMI;
Contents = MO.Contents;
TargetFlags = MO.TargetFlags;
return *this;
}

View File

@ -150,7 +150,9 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
/// isIdenticalTo - Return true if this operand is identical to the specified
/// operand.
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
if (getType() != Other.getType()) return false;
if (getType() != Other.getType() ||
getTargetFlags() != Other.getTargetFlags())
return false;
switch (getType()) {
default: assert(0 && "Unrecognized operand type");
@ -205,70 +207,72 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
}
if (getSubReg() != 0) {
OS << ":" << getSubReg();
OS << ':' << getSubReg();
}
if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
OS << "<";
OS << '<';
bool NeedComma = false;
if (isImplicit()) {
if (NeedComma) OS << ",";
if (NeedComma) OS << ',';
OS << (isDef() ? "imp-def" : "imp-use");
NeedComma = true;
} else if (isDef()) {
if (NeedComma) OS << ",";
if (NeedComma) OS << ',';
if (isEarlyClobber())
OS << "earlyclobber,";
OS << "def";
NeedComma = true;
}
if (isKill() || isDead()) {
if (NeedComma) OS << ",";
if (NeedComma) OS << ',';
if (isKill()) OS << "kill";
if (isDead()) OS << "dead";
}
OS << ">";
OS << '>';
}
break;
case MachineOperand::MO_Immediate:
OS << getImm();
break;
case MachineOperand::MO_FPImmediate:
if (getFPImm()->getType() == Type::FloatTy) {
if (getFPImm()->getType() == Type::FloatTy)
OS << getFPImm()->getValueAPF().convertToFloat();
} else {
else
OS << getFPImm()->getValueAPF().convertToDouble();
}
break;
case MachineOperand::MO_MachineBasicBlock:
OS << "mbb<"
<< ((Value*)getMBB()->getBasicBlock())->getName()
<< "," << (void*)getMBB() << ">";
<< "," << (void*)getMBB() << '>';
break;
case MachineOperand::MO_FrameIndex:
OS << "<fi#" << getIndex() << ">";
OS << "<fi#" << getIndex() << '>';
break;
case MachineOperand::MO_ConstantPoolIndex:
OS << "<cp#" << getIndex();
if (getOffset()) OS << "+" << getOffset();
OS << ">";
OS << '>';
break;
case MachineOperand::MO_JumpTableIndex:
OS << "<jt#" << getIndex() << ">";
OS << "<jt#" << getIndex() << '>';
break;
case MachineOperand::MO_GlobalAddress:
OS << "<ga:" << ((Value*)getGlobal())->getName();
if (getOffset()) OS << "+" << getOffset();
OS << ">";
OS << '>';
break;
case MachineOperand::MO_ExternalSymbol:
OS << "<es:" << getSymbolName();
if (getOffset()) OS << "+" << getOffset();
OS << ">";
OS << '>';
break;
default:
assert(0 && "Unrecognized operand type");
}
if (unsigned TF = getTargetFlags())
OS << "[TF=" << TF << ']';
}
//===----------------------------------------------------------------------===//
@ -1104,13 +1108,13 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg,
// If not found, this means an alias of one of the operands is dead. Add a
// new implicit operand if required.
if (!Found && AddIfNotFound) {
addOperand(MachineOperand::CreateReg(IncomingReg,
true /*IsDef*/,
true /*IsImp*/,
false /*IsKill*/,
true /*IsDead*/));
return true;
}
return Found;
if (Found || !AddIfNotFound)
return Found;
addOperand(MachineOperand::CreateReg(IncomingReg,
true /*IsDef*/,
true /*IsImp*/,
false /*IsKill*/,
true /*IsDead*/));
return true;
}