From 31ab4e43f9f55d449e47ffb40303bedff9021231 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 24 Jul 2019 16:53:14 +0000 Subject: [PATCH] [SelectionDAG] makeEquivalentMemoryOrdering - early out for equal chains (PR42727) If we are already using the same chain for the old/new memory ops then just return. Fixes PR42727 which had getLoad() reusing an existing node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366922 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +- test/CodeGen/X86/pr42727.ll | 34 +++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/pr42727.ll diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 5852e693fa9..ee9d13c5c2c 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -8619,7 +8619,7 @@ SDValue SelectionDAG::makeEquivalentMemoryOrdering(LoadSDNode *OldLoad, // TokenFactor. SDValue OldChain = SDValue(OldLoad, 1); SDValue NewChain = SDValue(NewMemOp.getNode(), 1); - if (!OldLoad->hasAnyUseOfValue(1)) + if (OldChain == NewChain || !OldLoad->hasAnyUseOfValue(1)) return NewChain; SDValue TokenFactor = diff --git a/test/CodeGen/X86/pr42727.ll b/test/CodeGen/X86/pr42727.ll new file mode 100644 index 00000000000..6b4a967f3f3 --- /dev/null +++ b/test/CodeGen/X86/pr42727.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-w64-windows-gnu | FileCheck %s + +%union.c_v256.26.65.104.143.962.1248 = type { [4 x i64] } + +define void @_ZN14simd_test_avx216c_imm_v256_alignILi1EEE6c_v256S1_S1_(%union.c_v256.26.65.104.143.962.1248* byval(%union.c_v256.26.65.104.143.962.1248) align 4) #0 { +; CHECK-LABEL: _ZN14simd_test_avx216c_imm_v256_alignILi1EEE6c_v256S1_S1_: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmovdqu {{[0-9]+}}(%esp), %xmm0 +; CHECK-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 +; CHECK-NEXT: vpsllq $56, %ymm0, %ymm0 +; CHECK-NEXT: vmovdqu %ymm0, (%eax) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retl +entry: + %b.sroa.0.sroa.2.0.b.sroa.0.0..sroa_cast.sroa_idx38 = getelementptr inbounds %union.c_v256.26.65.104.143.962.1248, %union.c_v256.26.65.104.143.962.1248* %0, i32 0, i32 0, i32 1 + %1 = bitcast i64* %b.sroa.0.sroa.2.0.b.sroa.0.0..sroa_cast.sroa_idx38 to <2 x i64>* + %2 = load <2 x i64>, <2 x i64>* %1, align 4 + %b.sroa.0.sroa.4.0.copyload = load i64, i64* undef, align 4 + %3 = extractelement <2 x i64> %2, i32 0 + %4 = extractelement <2 x i64> %2, i32 1 + %5 = insertelement <4 x i64> undef, i64 %3, i32 0 + %6 = insertelement <4 x i64> %5, i64 %4, i32 1 + %7 = insertelement <4 x i64> %6, i64 %b.sroa.0.sroa.4.0.copyload, i32 2 + %8 = insertelement <4 x i64> %7, i64 undef, i32 3 + %9 = shl <4 x i64> %8, + %10 = or <4 x i64> %9, zeroinitializer + store <4 x i64> %10, <4 x i64>* undef, align 8 + ret void +} + +attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+avx,+avx2,+cx8,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "unsafe-fp-math"="false" "use-soft-float"="false" } +