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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jia Liu 2012-02-18 12:03:15 +00:00
parent 107506f814
commit 31d157ae1a
293 changed files with 385 additions and 384 deletions
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2
lib/Target/ARM/ARM.h
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//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
//===-- ARM.h - Top-level interface for ARM representation-------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARM.td
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//===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMAsmPrinter.h
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@ -1,4 +1,4 @@
//===-- ARMAsmPrinter.h - Print machine code to an ARM .s file ------------===//
//===-- ARMAsmPrinter.h - Print machine code to an ARM .s file --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -1,4 +1,4 @@
//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMBaseInstrInfo.h
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@ -1,4 +1,4 @@
//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -1,4 +1,4 @@
//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMBaseRegisterInfo.h
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@ -1,4 +1,4 @@
//===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMBuildAttrs.h
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@ -1,4 +1,4 @@
//===-------- ARMBuildAttrs.h - ARM Build Attributes ------------*- C++ -*-===//
//===-- ARMBuildAttrs.h - ARM Build Attributes ------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMCallingConv.h
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@ -1,4 +1,4 @@
//===-- ARMCallingConv.h - ARM Custom Calling Convention Routines ---------===//
//=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMCallingConv.td
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@ -1,4 +1,4 @@
//===- ARMCallingConv.td - Calling Conventions for ARM -----*- tablegen -*-===//
//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMConstantPoolValue.cpp
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@ -1,4 +1,4 @@
//===- ARMConstantPoolValue.cpp - ARM constantpool value --------*- C++ -*-===//
//===-- ARMConstantPoolValue.cpp - ARM constantpool value -----------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMConstantPoolValue.h
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@ -1,4 +1,4 @@
//===- ARMConstantPoolValue.h - ARM constantpool value ----------*- C++ -*-===//
//===-- ARMConstantPoolValue.h - ARM constantpool value ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -1,4 +1,4 @@
//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMFrameLowering.cpp
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@ -1,4 +1,4 @@
//=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====//
//===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMInstrFormats.td
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@ -1,4 +1,4 @@
//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMInstrInfo.cpp
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@ -1,4 +1,4 @@
//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
//===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMInstrInfo.h
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@ -1,4 +1,4 @@
//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
//===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMInstrNEON.td
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@ -1,4 +1,4 @@
//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
//===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMInstrThumb.td
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@ -1,4 +1,4 @@
//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMInstrThumb2.td
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@ -1,4 +1,4 @@
//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
//===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMInstrVFP.td
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@ -1,4 +1,4 @@
//===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMJITInfo.h
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@ -1,4 +1,4 @@
//===- ARMJITInfo.h - ARM implementation of the JIT interface --*- C++ -*-===//
//===-- ARMJITInfo.h - ARM implementation of the JIT interface -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -1,4 +1,4 @@
//===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ----*- C++ -*-=//
//===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMMachineFunctionInfo.cpp
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@ -1,4 +1,4 @@
//====- ARMMachineFuctionInfo.cpp - ARM machine function info ---*- C++ -*-===//
//===-- ARMMachineFuctionInfo.cpp - ARM machine function info -------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMMachineFunctionInfo.h
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@ -1,4 +1,4 @@
//====- ARMMachineFuctionInfo.h - ARM machine function info -----*- C++ -*-===//
//===-- ARMMachineFuctionInfo.h - ARM machine function info -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMPerfectShuffle.h
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@ -1,4 +1,4 @@
//===-- ARMPerfectShuffle.h - NEON Perfect Shuffle Table ------------------===//
//===-- ARMPerfectShuffle.h - NEON Perfect Shuffle Table --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMRegisterInfo.cpp
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@ -1,4 +1,4 @@
//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
//===-- ARMRegisterInfo.cpp - ARM Register Information --------------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMRegisterInfo.h
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@ -1,4 +1,4 @@
//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
//===-- ARMRegisterInfo.h - ARM Register Information Impl -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMRegisterInfo.td
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@ -1,4 +1,4 @@
//===- ARMRegisterInfo.td - ARM Register defs --------------*- tablegen -*-===//
//===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMRelocations.h
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@ -1,4 +1,4 @@
//===- ARMRelocations.h - ARM Code Relocations ------------------*- C++ -*-===//
//===-- ARMRelocations.h - ARM Code Relocations -----------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

6
lib/Target/ARM/ARMSchedule.td
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@ -1,10 +1,10 @@
//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
//
//===-- ARMSchedule.td - ARM Scheduling Definitions --------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

6
lib/Target/ARM/ARMScheduleV6.td
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@ -1,10 +1,10 @@
//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
//
//===-- ARMScheduleV6.td - ARM v6 Scheduling Definitions ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the ARM v6 processors.

2
lib/Target/ARM/ARMSubtarget.cpp
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@ -1,4 +1,4 @@
//===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/ARMSubtarget.h
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@ -1,4 +1,4 @@
//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1,4 +1,4 @@
//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
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@ -1,4 +1,4 @@
//===-- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax ----------===//
//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
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@ -1,4 +1,4 @@
//===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
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@ -1,4 +1,4 @@
//===-- ARMMCAsmInfo.cpp - ARM asm properties -------------------*- C++ -*-===//
//===-- ARMMCAsmInfo.cpp - ARM asm properties -----------------------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
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@ -1,4 +1,4 @@
//=====-- ARMMCAsmInfo.h - ARM asm properties -------------*- C++ -*--====//
//===-- ARMMCAsmInfo.h - ARM asm properties --------------------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
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@ -1,4 +1,4 @@
//===-- ARMMCExpr.h - ARM specific MC expression classes ------------------===//
//===-- ARMMCExpr.h - ARM specific MC expression classes --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
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@ -1,4 +1,4 @@
//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===//
//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/MLxExpansionPass.cpp
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@ -1,4 +1,4 @@
//===-- MLxExpansionPass.cpp - Expand MLx instrs to avoid hazards ----------=//
//===-- MLxExpansionPass.cpp - Expand MLx instrs to avoid hazards ---------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Thumb1FrameLowering.cpp
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@ -1,4 +1,4 @@
//======- Thumb1FrameLowering.cpp - Thumb1 Frame Information ---*- C++ -*-====//
//===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Thumb1InstrInfo.cpp
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@ -1,4 +1,4 @@
//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Thumb1InstrInfo.h
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@ -1,4 +1,4 @@
//===- Thumb1InstrInfo.h - Thumb-1 Instruction Information ------*- C++ -*-===//
//===-- Thumb1InstrInfo.h - Thumb-1 Instruction Information -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Thumb1RegisterInfo.cpp
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@ -1,4 +1,4 @@
//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
//===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Thumb2ITBlockPass.cpp
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@ -1,4 +1,4 @@
//===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
//===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Thumb2InstrInfo.cpp
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@ -1,4 +1,4 @@
//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
//===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Thumb2InstrInfo.h
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@ -1,4 +1,4 @@
//===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===//
//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/ARM/Thumb2RegisterInfo.cpp
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@ -1,4 +1,4 @@
//===- Thumb2RegisterInfo.cpp - Thumb-2 Register Information ----*- C++ -*-===//
//===-- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/CellSDKIntrinsics.td
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@ -1,5 +1,5 @@
//===-- CellSDKIntrinsics.td - Cell SDK Intrinsics ---------*- tablegen -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source

2
lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp
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@ -1,4 +1,4 @@
//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===//
//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions ----------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/SPU.h
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@ -1,4 +1,4 @@
//===-- SPU.h - Top-level interface for Cell SPU Target ----------*- C++ -*-==//
//===-- SPU.h - Top-level interface for Cell SPU Target ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

4
lib/Target/CellSPU/SPU.td
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@ -1,5 +1,5 @@
//===- SPU.td - Describe the STI Cell SPU Target Machine ----*- tablegen -*-===//
//
//===-- SPU.td - Describe the STI Cell SPU Target Machine --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source

4
lib/Target/CellSPU/SPU128InstrInfo.td
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@ -1,9 +1,9 @@
//===--- SPU128InstrInfo.td - Cell SPU 128-bit operations -*- tablegen -*--===//
//===-- SPU128InstrInfo.td - Cell SPU 128-bit operations --*- tablegen -*--===//
//
// Cell SPU 128-bit operations
//
//===----------------------------------------------------------------------===//
// zext 32->128: Zero extend 32-bit to 128-bit
def : Pat<(i128 (zext R32C:$rSrc)),
(ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>;

2
lib/Target/CellSPU/SPU64InstrInfo.td
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@ -1,4 +1,4 @@
//====--- SPU64InstrInfo.td - Cell SPU 64-bit operations -*- tablegen -*--====//
//====-- SPU64InstrInfo.td - Cell SPU 64-bit operations ---*- tablegen -*--===//
//
// Cell SPU 64-bit operations
//

2
lib/Target/CellSPU/SPUAsmPrinter.cpp
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@ -1,4 +1,4 @@
//===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -------=//
//===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -----===//
//
// The LLVM Compiler Infrastructure
//

4
lib/Target/CellSPU/SPUCallingConv.td
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@ -1,10 +1,10 @@
//===- SPUCallingConv.td - Calling Conventions for CellSPU -*- tablegen -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This describes the calling conventions for the STI Cell SPU architecture.

2
lib/Target/CellSPU/SPUFrameLowering.h
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@ -1,4 +1,4 @@
//=====-- SPUFrameLowering.h - SPU Frame Lowering stuff -*- C++ -*----========//
//===-- SPUFrameLowering.h - SPU Frame Lowering stuff ----------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/SPUInstrBuilder.h
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@ -1,4 +1,4 @@
//==-- SPUInstrBuilder.h - Aides for building Cell SPU insts -----*- C++ -*-==//
//===-- SPUInstrBuilder.h - Aides for building Cell SPU insts ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

6
lib/Target/CellSPU/SPUInstrFormats.td
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@ -1,10 +1,10 @@
//==== SPUInstrFormats.td - Cell SPU Instruction Formats ---*- tablegen -*-===//
//
//===-- SPUInstrFormats.td - Cell SPU Instruction Formats --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

2
lib/Target/CellSPU/SPUInstrInfo.cpp
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@ -1,4 +1,4 @@
//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
//===-- SPUInstrInfo.cpp - Cell SPU Instruction Information ---------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/SPUInstrInfo.h
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@ -1,4 +1,4 @@
//===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
//===-- SPUInstrInfo.h - Cell SPU Instruction Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/SPUMachineFunction.cpp
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@ -1,4 +1,4 @@
//==-- SPUMachineFunctionInfo.cpp - Private data used for CellSPU -*- C++ -*-=//
//==-- SPUMachineFunctionInfo.cpp - Private data used for CellSPU ---------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/SPUMathInstr.td
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@ -1,4 +1,4 @@
//======--- SPUMathInst.td - Cell SPU math operations -*- tablegen -*---======//
//===-- SPUMathInst.td - Cell SPU math operations ---------*- tablegen -*--===//
//
// Cell SPU math operations
//

2
lib/Target/CellSPU/SPUNodes.td
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@ -1,4 +1,4 @@
//===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
//=== SPUNodes.td - Specialized SelectionDAG nodes by CellSPU -*- tablegen -*-//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/SPUNopFiller.cpp
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@ -1,4 +1,4 @@
//===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines---===//
//===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines ----------===//
//
// The LLVM Compiler Infrastructure
//

6
lib/Target/CellSPU/SPUOperands.td
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@ -1,10 +1,10 @@
//===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
//
//===-- SPUOperands.td - Cell SPU Instruction Operands -----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
// Cell SPU Instruction Operands:
//===----------------------------------------------------------------------===//

2
lib/Target/CellSPU/SPURegisterInfo.cpp
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@ -1,4 +1,4 @@
//===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
//===-- SPURegisterInfo.cpp - Cell SPU Register Information ---------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/SPURegisterInfo.h
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@ -1,4 +1,4 @@
//===- SPURegisterInfo.h - Cell SPU Register Information Impl ----*- C++ -*-==//
//===-- SPURegisterInfo.h - Cell SPU Register Information Impl --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

6
lib/Target/CellSPU/SPURegisterInfo.td
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@ -1,10 +1,10 @@
//===- SPURegisterInfo.td - The Cell SPU Register File -----*- tablegen -*-===//
//
//===-- SPURegisterInfo.td - The Cell SPU Register File ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
//

6
lib/Target/CellSPU/SPUSchedule.td
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@ -1,10 +1,10 @@
//===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===//
//
//===-- SPUSchedule.td - Cell Scheduling Definitions -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

2
lib/Target/CellSPU/SPUSubtarget.cpp
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@ -1,4 +1,4 @@
//===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
//===-- SPUSubtarget.cpp - STI Cell SPU Subtarget Information -------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/CellSPU/SPUTargetMachine.h
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@ -1,4 +1,4 @@
//===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU ----*- C++ -*-=//
//===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

6
lib/Target/Hexagon/Hexagon.td
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@ -1,4 +1,4 @@
//===- Hexagon.td - Describe the Hexagon Target Machine ---------*- C++ -*-===//
//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
//
// The LLVM Compiler Infrastructure
//
@ -7,6 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This is the top level entry point for the Hexagon target.
//
//===----------------------------------------------------------------------===//
@ -18,8 +19,7 @@ include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Hexagon Subtarget features.
//
//===----------------------------------------------------------------------===//
// Hexagon Archtectures
def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",

2
lib/Target/Hexagon/HexagonAsmPrinter.cpp
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@ -1,4 +1,4 @@
//===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ----=//
//===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonCFGOptimizer.cpp
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@ -1,4 +1,4 @@
//===---- HexagonCFGOptimizer.cpp - CFG optimizations ---------------------===//
//===-- HexagonCFGOptimizer.cpp - CFG optimizations -----------------------===//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source

4
lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
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@ -1,11 +1,11 @@
//===- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code -------===//
//===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===////
//===----------------------------------------------------------------------===//
// The Hexagon processor has no instructions that load or store predicate
// registers directly. So, when these registers must be spilled a general
// purpose register must be found and the value copied to/from it from/to

2
lib/Target/Hexagon/HexagonFrameLowering.cpp
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@ -1,4 +1,4 @@
//===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
//===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -1,4 +1,4 @@
//==-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon ----==//
//===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonISelLowering.h
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@ -1,4 +1,4 @@
//==-- HexagonISelLowering.h - Hexagon DAG Lowering Interface ----*- C++ -*-==//
//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonImmediates.td
View File

@ -1,4 +1,4 @@
//=- HexagonImmediates.td - Hexagon immediate processing --*- tablegen -*-=//
//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

16
lib/Target/Hexagon/HexagonInstrFormats.td
View File

@ -7,16 +7,16 @@
//
//===----------------------------------------------------------------------===//
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
// Hexagon Intruction Flags +
//
// *** Must match HexagonBaseInfo.h ***
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
// Intruction Class Declaration +
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr, InstrItinClass itin> : Instruction {
@ -40,9 +40,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
// *** The code above must match HexagonBaseInfo.h ***
}
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
// Intruction Classes Definitions +
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
// LD Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
@ -188,9 +188,9 @@ class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>;
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
// Intruction Classes Definitions -
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
//

2
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1,4 +1,4 @@
//===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonInstrInfo.h
View File

@ -1,4 +1,4 @@
//=- HexagonInstrInfo.h - Hexagon Instruction Information ---------*- C++ -*-=//
//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonIntrinsics.td
View File

@ -1,4 +1,4 @@
//===- HexagonIntrinsics.td - Instruction intrinsics -------*- tablegen -*-===//
//===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -1,4 +1,4 @@
//===- HexagonRegisterInfo.cpp - Hexagon Register Information -------------===//
//===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonRegisterInfo.td
View File

@ -1,4 +1,4 @@
//===- HexagonRegisterInfo.td - Hexagon Register defs ------*- tablegen -*-===//
//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonSchedule.td
View File

@ -1,4 +1,4 @@
//===-HexagonSchedule.td - Hexagon Scheduling Definitions -------*- C++ -*-===//
//===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonSelectCCInfo.td
View File

@ -1,4 +1,4 @@
//=-HexagoSelectCCInfo.td - Selectcc mappings ----------------*- tablegen -*-=//
//===-- HexagoSelectCCInfo.td - Selectcc mappings ----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonSelectionDAGInfo.h
View File

@ -1,4 +1,4 @@
//=-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ------*- C++ -*-=//
//===-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

4
lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp
View File

@ -1,4 +1,4 @@
//===---- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -----===//
//===-- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -------===//
//
// The LLVM Compiler Infrastructure
//
@ -6,7 +6,7 @@
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===////
//===----------------------------------------------------------------------===//
// This pass tries to provide opportunities for better optimization of muxes.
// The default code generated for something like: flag = (a == b) ? 1 : 3;
// would be:

2
lib/Target/Hexagon/HexagonSubtarget.cpp
View File

@ -1,4 +1,4 @@
//===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonSubtarget.h
View File

@ -1,4 +1,4 @@
//==-- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-==//
//===-- HexagonSubtarget.h - Define Subtarget for the Hexagon ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

3
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -1,4 +1,4 @@
//===- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon --------===//
//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,6 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// Implements the info about Hexagon target spec.
//
//===----------------------------------------------------------------------===//

2
lib/Target/Hexagon/HexagonTargetObjectFile.cpp
View File

@ -1,4 +1,4 @@
//===-- HexagonTargetObjectFile.cpp - Hexagon asm properties ----*- C++ -*-===//
//===-- HexagonTargetObjectFile.cpp - Hexagon asm properties --------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonTargetObjectFile.h
View File

@ -1,4 +1,4 @@
//===-- HexagonTargetAsmInfo.h - Hexagon asm properties ---------*- C++ -*--==//
//===-- HexagonTargetAsmInfo.h - Hexagon asm properties --------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/HexagonVarargsCallingConvention.h
View File

@ -1,4 +1,4 @@
//==-- HexagonVarargsCallingConvention.h - Calling Conventions ---*- C++ -*-==//
//===-- HexagonVarargsCallingConvention.h - Calling Conventions -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
View File

@ -1,4 +1,4 @@
//===-- HexagonBaseInfo.h - Top level definitions for Hexagon -------------===//
//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- HexagonMCAsmInfo.cpp - Hexagon asm properties -----------*- C++ -*-===//
//===-- HexagonMCAsmInfo.cpp - Hexagon asm properties ---------------------===//
//
// The LLVM Compiler Infrastructure
//

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