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Implement SetCC, fix ZERO_EXTEND_INREG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20933 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -587,7 +587,6 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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case ISD::SUB: Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS; break;
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case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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@ -865,8 +864,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case MVT::i8: Tmp2 = 24; break;
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case MVT::i1: Tmp2 = 31; break;
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}
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BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(0).addImm(0)
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.addImm(Tmp2).addImm(31);
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BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2)
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.addImm(31);
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return Result;
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case ISD::CopyFromReg:
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@ -880,7 +879,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Tmp1 = SelectExpr(N.getOperand(0));
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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Tmp2 = CN->getValue() & 0x1F;
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BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
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BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
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.addImm(31-Tmp2);
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} else {
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Tmp2 = SelectExpr(N.getOperand(1));
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@ -892,7 +891,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Tmp1 = SelectExpr(N.getOperand(0));
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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Tmp2 = CN->getValue() & 0x1F;
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BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(32-Tmp2)
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BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(32-Tmp2)
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.addImm(Tmp2).addImm(31);
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} else {
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Tmp2 = SelectExpr(N.getOperand(1));
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@ -1028,7 +1027,75 @@ unsigned ISel::SelectExpr(SDOperand N) {
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abort();
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case ISD::SETCC:
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abort();
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if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
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bool U = false;
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bool IsInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
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switch (SetCC->getCondition()) {
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default: Node->dump(); assert(0 && "Unknown comparison!");
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case ISD::SETEQ: Opc = PPC::BEQ; break;
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case ISD::SETNE: Opc = PPC::BNE; break;
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case ISD::SETULT: U = true;
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case ISD::SETLT: Opc = PPC::BLT; break;
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case ISD::SETULE: U = true;
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case ISD::SETLE: Opc = PPC::BLE; break;
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case ISD::SETUGT: U = true;
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case ISD::SETGT: Opc = PPC::BGT; break;
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case ISD::SETUGE: U = true;
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case ISD::SETGE: Opc = PPC::BGE; break;
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}
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// FIXME: Is there a situation in which we would ever need to emit fcmpo?
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static const unsigned CompareOpcodes[] =
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{ PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
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unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
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// Create an iterator with which to insert the MBB for copying the false
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// value and the MBB to hold the PHI instruction for this SetCC.
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// cmpTY cr0, r1, r2
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// %TrueValue = li 1
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// bCC sinkMBB
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, CompareOpc, 2, PPC::CR0).addReg(Tmp1).addReg(Tmp2);
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unsigned TrueValue = MakeReg(MVT::i32);
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BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = li 0
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// fallthrough
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BB = copy0MBB;
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unsigned FalseValue = MakeReg(MVT::i32);
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BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
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.addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
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return Result;
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}
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assert(0 && "Is this legal?");
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return 0;
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case ISD::SELECT:
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abort();
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@ -292,6 +292,8 @@ def CMPLW : XForm_16_ext<31, 32, 0, 0,
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def CMPLD : XForm_16_ext<31, 32, 1, 0,
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(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpld $crD, $rA, $rB">;
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def FCMPO : XForm_17<63, 32, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
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"fcmpo $crD, $fA, $fB">;
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def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
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"fcmpu $crD, $fA, $fB">;
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let isLoad = 1 in {
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