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[InstCombine] SSE/AVX vector shifts demanded shift amount bits
Most SSE/AVX (non-constant) vector shift instructions only use the lower 64-bits of the 128-bit shift amount vector operand, this patch calls SimplifyDemandedVectorElts to optimize for this. I had to refactor some of my recent InstCombiner work on the vector shifts to avoid quite a bit of duplicate code, it means that SimplifyX86immshift now (re)decodes the type of shift. Differential Revision: http://reviews.llvm.org/D11938 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244872 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
d4177b2705
commit
335fc61873
@ -198,8 +198,52 @@ Instruction *InstCombiner::SimplifyMemSet(MemSetInst *MI) {
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}
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static Value *SimplifyX86immshift(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder,
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bool LogicalShift, bool ShiftLeft) {
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InstCombiner::BuilderTy &Builder) {
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bool LogicalShift = false;
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bool ShiftLeft = false;
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switch (II.getIntrinsicID()) {
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default:
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return nullptr;
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case Intrinsic::x86_sse2_psra_d:
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case Intrinsic::x86_sse2_psra_w:
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case Intrinsic::x86_sse2_psrai_d:
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case Intrinsic::x86_sse2_psrai_w:
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case Intrinsic::x86_avx2_psra_d:
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case Intrinsic::x86_avx2_psra_w:
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case Intrinsic::x86_avx2_psrai_d:
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case Intrinsic::x86_avx2_psrai_w:
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LogicalShift = false; ShiftLeft = false;
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break;
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case Intrinsic::x86_sse2_psrl_d:
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case Intrinsic::x86_sse2_psrl_q:
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case Intrinsic::x86_sse2_psrl_w:
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case Intrinsic::x86_sse2_psrli_d:
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case Intrinsic::x86_sse2_psrli_q:
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case Intrinsic::x86_sse2_psrli_w:
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case Intrinsic::x86_avx2_psrl_d:
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case Intrinsic::x86_avx2_psrl_q:
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case Intrinsic::x86_avx2_psrl_w:
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case Intrinsic::x86_avx2_psrli_d:
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case Intrinsic::x86_avx2_psrli_q:
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case Intrinsic::x86_avx2_psrli_w:
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LogicalShift = true; ShiftLeft = false;
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break;
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case Intrinsic::x86_sse2_psll_d:
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case Intrinsic::x86_sse2_psll_q:
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case Intrinsic::x86_sse2_psll_w:
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case Intrinsic::x86_sse2_pslli_d:
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case Intrinsic::x86_sse2_pslli_q:
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case Intrinsic::x86_sse2_pslli_w:
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case Intrinsic::x86_avx2_psll_d:
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case Intrinsic::x86_avx2_psll_q:
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case Intrinsic::x86_avx2_psll_w:
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case Intrinsic::x86_avx2_pslli_d:
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case Intrinsic::x86_avx2_pslli_q:
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case Intrinsic::x86_avx2_pslli_w:
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LogicalShift = true; ShiftLeft = true;
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break;
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}
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assert((LogicalShift || !ShiftLeft) && "Only logical shifts can shift left");
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// Simplify if count is constant.
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@ -788,52 +832,65 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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}
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// Constant fold ashr( <A x Bi>, Ci ).
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case Intrinsic::x86_sse2_psra_d:
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case Intrinsic::x86_sse2_psra_w:
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// Constant fold lshr( <A x Bi>, Ci ).
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// Constant fold shl( <A x Bi>, Ci ).
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case Intrinsic::x86_sse2_psrai_d:
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case Intrinsic::x86_sse2_psrai_w:
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case Intrinsic::x86_avx2_psra_d:
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case Intrinsic::x86_avx2_psra_w:
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case Intrinsic::x86_avx2_psrai_d:
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case Intrinsic::x86_avx2_psrai_w:
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if (Value *V = SimplifyX86immshift(*II, *Builder, false, false))
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return ReplaceInstUsesWith(*II, V);
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break;
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// Constant fold lshr( <A x Bi>, Ci ).
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case Intrinsic::x86_sse2_psrl_d:
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case Intrinsic::x86_sse2_psrl_q:
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case Intrinsic::x86_sse2_psrl_w:
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case Intrinsic::x86_sse2_psrli_d:
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case Intrinsic::x86_sse2_psrli_q:
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case Intrinsic::x86_sse2_psrli_w:
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case Intrinsic::x86_avx2_psrl_d:
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case Intrinsic::x86_avx2_psrl_q:
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case Intrinsic::x86_avx2_psrl_w:
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case Intrinsic::x86_avx2_psrli_d:
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case Intrinsic::x86_avx2_psrli_q:
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case Intrinsic::x86_avx2_psrli_w:
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if (Value *V = SimplifyX86immshift(*II, *Builder, true, false))
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return ReplaceInstUsesWith(*II, V);
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break;
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// Constant fold shl( <A x Bi>, Ci ).
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case Intrinsic::x86_sse2_psll_d:
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case Intrinsic::x86_sse2_psll_q:
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case Intrinsic::x86_sse2_psll_w:
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case Intrinsic::x86_sse2_pslli_d:
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case Intrinsic::x86_sse2_pslli_q:
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case Intrinsic::x86_sse2_pslli_w:
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case Intrinsic::x86_avx2_psll_d:
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case Intrinsic::x86_avx2_psll_q:
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case Intrinsic::x86_avx2_psll_w:
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case Intrinsic::x86_avx2_pslli_d:
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case Intrinsic::x86_avx2_pslli_q:
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case Intrinsic::x86_avx2_pslli_w:
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if (Value *V = SimplifyX86immshift(*II, *Builder, true, true))
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if (Value *V = SimplifyX86immshift(*II, *Builder))
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return ReplaceInstUsesWith(*II, V);
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break;
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case Intrinsic::x86_sse2_psra_d:
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case Intrinsic::x86_sse2_psra_w:
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case Intrinsic::x86_avx2_psra_d:
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case Intrinsic::x86_avx2_psra_w:
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case Intrinsic::x86_sse2_psrl_d:
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case Intrinsic::x86_sse2_psrl_q:
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case Intrinsic::x86_sse2_psrl_w:
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case Intrinsic::x86_avx2_psrl_d:
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case Intrinsic::x86_avx2_psrl_q:
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case Intrinsic::x86_avx2_psrl_w:
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case Intrinsic::x86_sse2_psll_d:
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case Intrinsic::x86_sse2_psll_q:
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case Intrinsic::x86_sse2_psll_w:
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case Intrinsic::x86_avx2_psll_d:
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case Intrinsic::x86_avx2_psll_q:
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case Intrinsic::x86_avx2_psll_w: {
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if (Value *V = SimplifyX86immshift(*II, *Builder))
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return ReplaceInstUsesWith(*II, V);
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// SSE2/AVX2 uses only the first 64-bits of the 128-bit vector
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// operand to compute the shift amount.
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auto ShiftAmt = II->getArgOperand(1);
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auto ShiftType = cast<VectorType>(ShiftAmt->getType());
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assert(ShiftType->getPrimitiveSizeInBits() == 128 &&
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"Unexpected packed shift size");
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unsigned VWidth = ShiftType->getNumElements();
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APInt DemandedElts = APInt::getLowBitsSet(VWidth, VWidth / 2);
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APInt UndefElts(VWidth, 0);
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if (Value *V =
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SimplifyDemandedVectorElts(ShiftAmt, DemandedElts, UndefElts)) {
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II->setArgOperand(1, V);
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return II;
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}
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break;
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}
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case Intrinsic::x86_sse41_pmovsxbd:
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case Intrinsic::x86_sse41_pmovsxbq:
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case Intrinsic::x86_sse41_pmovsxbw:
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@ -825,6 +825,154 @@ define <4 x i64> @avx2_psll_q_64(<4 x i64> %v) nounwind readnone uwtable {
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ret <4 x i64> %1
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}
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;
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; Vector Demanded Bits
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;
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define <8 x i16> @sse2_psra_w_var(<8 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @sse2_psra_w_var
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; CHECK-NEXT: %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> %a)
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; CHECK-NEXT: ret <8 x i16> %1
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%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> %1)
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ret <8 x i16> %2
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}
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define <4 x i32> @sse2_psra_d_var(<4 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @sse2_psra_d_var
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; CHECK-NEXT: %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> %a)
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; CHECK-NEXT: ret <4 x i32> %1
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%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%2 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> %1)
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ret <4 x i32> %2
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}
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define <16 x i16> @avx2_psra_w_var(<16 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @avx2_psra_w_var
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; CHECK-NEXT: %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> %a)
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; CHECK-NEXT: ret <16 x i16> %1
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%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> %1)
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ret <16 x i16> %2
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}
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define <8 x i32> @avx2_psra_d_var(<8 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @avx2_psra_d_var
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; CHECK-NEXT: %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> %a)
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; CHECK-NEXT: ret <8 x i32> %1
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%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%2 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> %1)
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ret <8 x i32> %2
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}
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define <8 x i16> @sse2_psrl_w_var(<8 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @sse2_psrl_w_var
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; CHECK-NEXT: %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> %a)
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; CHECK-NEXT: ret <8 x i16> %1
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%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> %1)
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ret <8 x i16> %2
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}
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define <4 x i32> @sse2_psrl_d_var(<4 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @sse2_psrl_d_var
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; CHECK-NEXT: %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> %a)
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; CHECK-NEXT: ret <4 x i32> %1
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%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%2 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> %1)
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ret <4 x i32> %2
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}
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define <2 x i64> @sse2_psrl_q_var(<2 x i64> %v, <2 x i64> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @sse2_psrl_q_var
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; CHECK-NEXT: %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> %a)
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; CHECK-NEXT: ret <2 x i64> %1
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%1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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%2 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> %1)
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ret <2 x i64> %2
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}
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define <16 x i16> @avx2_psrl_w_var(<16 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @avx2_psrl_w_var
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; CHECK-NEXT: %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> %a)
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; CHECK-NEXT: ret <16 x i16> %1
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%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> %1)
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ret <16 x i16> %2
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}
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define <8 x i32> @avx2_psrl_d_var(<8 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @avx2_psrl_d_var
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; CHECK-NEXT: %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> %a)
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; CHECK-NEXT: ret <8 x i32> %1
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%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%2 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> %1)
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ret <8 x i32> %2
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}
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define <4 x i64> @avx2_psrl_q_var(<4 x i64> %v, <2 x i64> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @avx2_psrl_q_var
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; CHECK-NEXT: %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> %a)
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; CHECK-NEXT: ret <4 x i64> %1
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%1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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%2 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> %1)
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ret <4 x i64> %2
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}
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define <8 x i16> @sse2_psll_w_var(<8 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @sse2_psll_w_var
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; CHECK-NEXT: %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> %a)
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; CHECK-NEXT: ret <8 x i16> %1
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%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> %1)
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ret <8 x i16> %2
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}
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define <4 x i32> @sse2_psll_d_var(<4 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @sse2_psll_d_var
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; CHECK-NEXT: %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> %a)
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; CHECK-NEXT: ret <4 x i32> %1
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%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%2 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> %1)
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ret <4 x i32> %2
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}
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define <2 x i64> @sse2_psll_q_var(<2 x i64> %v, <2 x i64> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @sse2_psll_q_var
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; CHECK-NEXT: %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> %a)
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; CHECK-NEXT: ret <2 x i64> %1
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%1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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%2 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> %1)
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ret <2 x i64> %2
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}
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define <16 x i16> @avx2_psll_w_var(<16 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @avx2_psll_w_var
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; CHECK-NEXT: %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> %a)
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; CHECK-NEXT: ret <16 x i16> %1
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%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> %1)
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ret <16 x i16> %2
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}
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define <8 x i32> @avx2_psll_d_var(<8 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
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; CHECK-LABEL: @avx2_psll_d_var
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; CHECK-NEXT: %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> %a)
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; CHECK-NEXT: ret <8 x i32> %1
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%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%2 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> %1)
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ret <8 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i64> @avx2_psll_q_var(<4 x i64> %v, <2 x i64> %a) nounwind readnone uwtable {
|
||||
; CHECK-LABEL: @avx2_psll_q_var
|
||||
; CHECK-NEXT: %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> %a)
|
||||
; CHECK-NEXT: ret <4 x i64> %1
|
||||
%1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
|
||||
%2 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> %1)
|
||||
ret <4 x i64> %2
|
||||
}
|
||||
|
||||
;
|
||||
; Constant Folding
|
||||
;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user