diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index fa84f1cb261..abf71e3aab9 100644 --- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -228,6 +228,11 @@ public: return isClamp() || isOMod(); } + bool isGDS() const { return isImmTy(ImmTyGDS); } + bool isGLC() const { return isImmTy(ImmTyGLC); } + bool isSLC() const { return isImmTy(ImmTySLC); } + bool isTFE() const { return isImmTy(ImmTyTFE); } + void setModifiers(unsigned Mods) { assert(isReg() || (isImm() && Imm.Modifiers == 0)); if (isReg()) @@ -1732,7 +1737,7 @@ AMDGPUAsmParser::parseTFE(OperandVector &Operands) { } bool AMDGPUOperand::isMubufOffset() const { - return isImm() && isUInt<12>(getImm()); + return isImmTy(ImmTyOffset) && isUInt<12>(getImm()); } void AMDGPUAsmParser::cvtMubuf(MCInst &Inst, @@ -1933,38 +1938,26 @@ void AMDGPUAsmParser::cvtVOP3_only(MCInst &Inst, const OperandVector &Operands) } void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) { + OptionalImmIndexMap OptionalIdx; unsigned I = 1; const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); for (unsigned J = 0; J < Desc.getNumDefs(); ++J) { ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); } - unsigned ClampIdx = 0, OModIdx = 0; for (unsigned E = Operands.size(); I != E; ++I) { AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); if (Op.isRegOrImmWithInputMods()) { Op.addRegOrImmWithInputModsOperands(Inst, 2); - } else if (Op.isClamp()) { - ClampIdx = I; - } else if (Op.isOMod()) { - OModIdx = I; + } else if (Op.isImm()) { + OptionalIdx[Op.getImmTy()] = I; } else { assert(false); } } - if (ClampIdx) { - AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ClampIdx]); - Op.addImmOperands(Inst, 1); - } else { - Inst.addOperand(MCOperand::createImm(0)); - } - if (OModIdx) { - AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[OModIdx]); - Op.addImmOperands(Inst, 1); - } else { - Inst.addOperand(MCOperand::createImm(0)); - } + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClamp); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOMod); } void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) { diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index eda6223d001..9e3cc81a29f 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -463,7 +463,7 @@ def DSOffset01MatchClass : AsmOperandClass { class GDSBaseMatchClass : AsmOperandClass { let Name = "GDS"#parser; - let PredicateMethod = "isImm"; + let PredicateMethod = "isGDS"; let ParserMethod = parser; let RenderMethod = "addImmOperands"; let IsOptional = 1; @@ -474,7 +474,7 @@ def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">; class GLCBaseMatchClass : AsmOperandClass { let Name = "GLC"#parser; - let PredicateMethod = "isImm"; + let PredicateMethod = "isGLC"; let ParserMethod = parser; let RenderMethod = "addImmOperands"; let IsOptional = 1; @@ -485,7 +485,7 @@ def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">; class SLCBaseMatchClass : AsmOperandClass { let Name = "SLC"#parser; - let PredicateMethod = "isImm"; + let PredicateMethod = "isSLC"; let ParserMethod = parser; let RenderMethod = "addImmOperands"; let IsOptional = 1; @@ -497,7 +497,7 @@ def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">; class TFEBaseMatchClass : AsmOperandClass { let Name = "TFE"#parser; - let PredicateMethod = "isImm"; + let PredicateMethod = "isTFE"; let ParserMethod = parser; let RenderMethod = "addImmOperands"; let IsOptional = 1; @@ -509,7 +509,7 @@ def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">; def OModMatchClass : AsmOperandClass { let Name = "OMod"; - let PredicateMethod = "isImm"; + let PredicateMethod = "isOMod"; let ParserMethod = "parseVOP3OptionalOps"; let RenderMethod = "addImmOperands"; let IsOptional = 1; @@ -517,7 +517,7 @@ def OModMatchClass : AsmOperandClass { def ClampMatchClass : AsmOperandClass { let Name = "Clamp"; - let PredicateMethod = "isImm"; + let PredicateMethod = "isClamp"; let ParserMethod = "parseVOP3OptionalOps"; let RenderMethod = "addImmOperands"; let IsOptional = 1; diff --git a/test/MC/AMDGPU/flat.s b/test/MC/AMDGPU/flat.s index a6b8cdf6351..c6894c35f4d 100644 --- a/test/MC/AMDGPU/flat.s +++ b/test/MC/AMDGPU/flat.s @@ -40,61 +40,21 @@ flat_load_dword v1, v[3:4] glc slc tfe // CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] // VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01] -flat_load_dword v1, v[3:4] glc tfe slc -// NOSI: error: -// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] -// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01] - flat_load_dword v1, v[3:4] slc // NOSI: error: // CI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x00,0x01] // VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01] -flat_load_dword v1, v[3:4] slc glc -// NOSI: error: -// CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01] -// VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01] - flat_load_dword v1, v[3:4] slc tfe // NOSI: error: // CI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01] // VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01] -flat_load_dword v1, v[3:4] slc glc tfe -// NOSI: error: -// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] -// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01] - -flat_load_dword v1, v[3:4] slc tfe glc -// NOSI: error: -// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] -// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01] - flat_load_dword v1, v[3:4] tfe // NOSI: error: // CI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x80,0x01] // VI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x80,0x01] -flat_load_dword v1, v[3:4] tfe glc -// NOSI: error: -// CI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01] -// VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01] - -flat_load_dword v1, v[3:4] tfe slc -// NOSI: error: -// CI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01] -// VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01] - -flat_load_dword v1, v[3:4] tfe glc slc -// NOSI: error: -// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] -// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01] - -flat_load_dword v1, v[3:4] tfe slc glc -// NOSI: error: -// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] -// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01] - flat_store_dword v[3:4], v1 // NOSI: error: // CIVI: flat_store_dword v[3:4], v1 ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00] @@ -115,50 +75,18 @@ flat_store_dword v[3:4], v1 glc slc tfe // NOSI: error: // CIVI: flat_store_dword v[3:4], v1 glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] -flat_store_dword v[3:4], v1 glc tfe slc -// NOSI: error: -// CIVI: flat_store_dword v[3:4], v1 glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] - flat_store_dword v[3:4], v1 slc // NOSI: error: // CIVI: flat_store_dword v[3:4], v1 slc ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x00,0x00] -flat_store_dword v[3:4], v1 slc glc -// NOSI: error: -// CIVI: flat_store_dword v[3:4], v1 glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00] - flat_store_dword v[3:4], v1 slc tfe // NOSI: error: // CIVI: flat_store_dword v[3:4], v1 slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00] -flat_store_dword v[3:4], v1 slc glc tfe -// NOSI: error: -// CIVI: flat_store_dword v[3:4], v1 glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] - -flat_store_dword v[3:4], v1 slc tfe glc -// NOSI: error: -// CIVI: flat_store_dword v[3:4], v1 glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] - flat_store_dword v[3:4], v1 tfe // NOSI: error: // CIVI: flat_store_dword v[3:4], v1 tfe ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x80,0x00] -flat_store_dword v[3:4], v1 tfe glc -// NOSI: error: -// CIVI: flat_store_dword v[3:4], v1 glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00] - -flat_store_dword v[3:4], v1 tfe slc -// NOSI: error: -// CIVI: flat_store_dword v[3:4], v1 slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00] - -flat_store_dword v[3:4], v1 tfe glc slc -// NOSI: error: -// CIVI: flat_store_dword v[3:4], v1 glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] - -flat_store_dword v[3:4], v1 tfe slc glc -// NOSI: error: -// CIVI: flat_store_dword v[3:4], v1 glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] - // FIXME: For atomic instructions, glc must be placed immediately following // the data regiser. These forms aren't currently supported: // flat_atomic_add v1, v[3:4], v5 slc glc @@ -184,11 +112,6 @@ flat_atomic_add v1 v[3:4], v5 glc slc tfe // CI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01] // VI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x80,0x01] -flat_atomic_add v1 v[3:4], v5 glc tfe slc -// NOSI: error: -// CI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01] -// VI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x80,0x01] - flat_atomic_add v[3:4], v5 slc // NOSI: error: // CI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x00,0x00] @@ -471,8 +394,8 @@ flat_atomic_umin_x2 v[3:4], v[5:6] flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc // NOSI: error: -// CI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x59,0xdd,0x03,0x05,0x00,0x01] -// VI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x95,0xdd,0x03,0x05,0x00,0x01] +// CI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x59,0xdd,0x03,0x05,0x00,0x01] +// VI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x95,0xdd,0x03,0x05,0x00,0x01] flat_atomic_smax_x2 v[3:4], v[5:6] // NOSI: error: diff --git a/test/MC/AMDGPU/mubuf.s b/test/MC/AMDGPU/mubuf.s index 18cca702269..a865f72c11f 100644 --- a/test/MC/AMDGPU/mubuf.s +++ b/test/MC/AMDGPU/mubuf.s @@ -28,13 +28,10 @@ buffer_load_dword v1, s[4:7], s1 offset:4 slc buffer_load_dword v1, s[4:7], s1 offset:4 tfe // SICI: buffer_load_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x81,0x01] -buffer_load_dword v1, s[4:7], s1 tfe glc +buffer_load_dword v1, s[4:7], s1 glc tfe // SICI: buffer_load_dword v1, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x30,0xe0,0x00,0x01,0x81,0x01] -buffer_load_dword v1, s[4:7], s1 offset:4 glc tfe slc -// SICI: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01] - -buffer_load_dword v1, s[4:7], s1 glc tfe slc offset:4 +buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe // SICI: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -56,13 +53,10 @@ buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 tfe // SICI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x81,0x01] -buffer_load_dword v1, v2, s[4:7], s1 offen tfe glc +buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe // SICI: buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x30,0xe0,0x02,0x01,0x81,0x01] -buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc -// SICI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01] - -buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4 +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe // SICI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -84,13 +78,10 @@ buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe // SICI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x81,0x01] -buffer_load_dword v1, v2, s[4:7], s1 idxen tfe glc +buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe // SICI: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x30,0xe0,0x02,0x01,0x81,0x01] -buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc -// SICI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01] - -buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4 +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe // SICI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -112,13 +103,10 @@ buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x81,0x01] -buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x30,0xe0,0x02,0x01,0x81,0x01] -buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc -// SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01] - -buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4 +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -140,13 +128,10 @@ buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x81,0x01] -buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x30,0xe0,0x02,0x01,0x81,0x01] -buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc -// SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01] - -buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4 +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -168,13 +153,10 @@ buffer_store_dword v1, s[4:7], s1 offset:4 slc buffer_store_dword v1, s[4:7], s1 offset:4 tfe // SICI: buffer_store_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01] -buffer_store_dword v1, s[4:7], s1 tfe glc +buffer_store_dword v1, s[4:7], s1 glc tfe // SICI: buffer_store_dword v1, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x70,0xe0,0x00,0x01,0x81,0x01] -buffer_store_dword v1, s[4:7], s1 offset:4 glc tfe slc -// SICI: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01] - -buffer_store_dword v1, s[4:7], s1 glc tfe slc offset:4 +buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe // SICI: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -196,13 +178,10 @@ buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x81,0x01] -buffer_store_dword v1, v2, s[4:7], s1 offen tfe glc +buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x70,0xe0,0x02,0x01,0x81,0x01] -buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc -// SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01] - -buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4 +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -224,13 +203,10 @@ buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x81,0x01] -buffer_store_dword v1, v2, s[4:7], s1 idxen tfe glc +buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x70,0xe0,0x02,0x01,0x81,0x01] -buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc -// SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01] - -buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4 +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -252,13 +228,10 @@ buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x81,0x01] -buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x70,0xe0,0x02,0x01,0x81,0x01] -buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc -// SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01] - -buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4 +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// @@ -280,13 +253,10 @@ buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x81,0x01] -buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x70,0xe0,0x02,0x01,0x81,0x01] -buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc -// SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01] - -buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4 +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01] //===----------------------------------------------------------------------===// diff --git a/test/MC/AMDGPU/vop3.s b/test/MC/AMDGPU/vop3.s index 6f9b2f7458f..f4b587f39f6 100644 --- a/test/MC/AMDGPU/vop3.s +++ b/test/MC/AMDGPU/vop3.s @@ -137,7 +137,7 @@ v_clrexcp_e64 // // Modifier tests: -// +// v_fract_f32 v1, -v2 // SICI: v_fract_f32_e64 v1, -v2 ; encoding: [0x01,0x00,0x40,0xd3,0x02,0x01,0x00,0x20] @@ -159,7 +159,7 @@ v_fract_f32 v1, v2 mul:2 // SICI: v_fract_f32_e64 v1, v2 mul:2 ; encoding: [0x01,0x00,0x40,0xd3,0x02,0x01,0x00,0x08] // VI: v_fract_f32_e64 v1, v2 mul:2 ; encoding: [0x01,0x00,0x5b,0xd1,0x02,0x01,0x00,0x08] -v_fract_f32 v1, v2, div:2 clamp +v_fract_f32 v1, v2, clamp div:2 // SICI: v_fract_f32_e64 v1, v2 clamp div:2 ; encoding: [0x01,0x08,0x40,0xd3,0x02,0x01,0x00,0x18] // VI: v_fract_f32_e64 v1, v2 clamp div:2 ; encoding: [0x01,0x80,0x5b,0xd1,0x02,0x01,0x00,0x18] diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index 103ed99e35c..799f20d0b94 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -3108,37 +3108,44 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { // Emit check that the subclasses match. OS << " bool OperandsValid = true;\n"; - OS << " for (unsigned i = " << (HasMnemonicFirst ? "0" : "SIndex") - << "; i != " << MaxNumOperands << "; ++i) {\n"; - OS << " auto Formal = static_cast(it->Classes[i]);\n"; - OS << " if (i" << (HasMnemonicFirst ? "+1" : "") - << " >= Operands.size()) {\n"; + OS << " for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex") + << ", ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex") + << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n"; + OS << " auto Formal = " + << "static_cast(it->Classes[FormalIdx]);\n"; + OS << " if (ActualIdx >= Operands.size()) {\n"; OS << " OperandsValid = (Formal == " <<"InvalidMatchClass) || " "isSubclass(Formal, OptionalMatchClass);\n"; - OS << " if (!OperandsValid) ErrorInfo = i" - << (HasMnemonicFirst ? "+1" : "") << ";\n"; + OS << " if (!OperandsValid) ErrorInfo = ActualIdx;\n"; OS << " break;\n"; OS << " }\n"; - OS << " MCParsedAsmOperand &Actual = *Operands[i" - << (HasMnemonicFirst ? "+1" : "") << "];\n"; + OS << " MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n"; OS << " unsigned Diag = validateOperandClass(Actual, Formal);\n"; - OS << " if (Diag == Match_Success)\n"; + OS << " if (Diag == Match_Success) {\n"; + OS << " ++ActualIdx;\n"; OS << " continue;\n"; + OS << " }\n"; OS << " // If the generic handler indicates an invalid operand\n"; OS << " // failure, check for a special case.\n"; OS << " if (Diag == Match_InvalidOperand) {\n"; OS << " Diag = validateTargetOperandClass(Actual, Formal);\n"; - OS << " if (Diag == Match_Success)\n"; + OS << " if (Diag == Match_Success) {\n"; + OS << " ++ActualIdx;\n"; OS << " continue;\n"; + OS << " }\n"; OS << " }\n"; + OS << " // If current formal operand wasn't matched and it is optional\n" + << " // then try to match next formal operand\n"; + OS << " if (Diag == Match_InvalidOperand " + << "&& isSubclass(Formal, OptionalMatchClass))\n"; + OS << " continue;\n"; OS << " // If this operand is broken for all of the instances of this\n"; OS << " // mnemonic, keep track of it so we can report loc info.\n"; OS << " // If we already had a match that only failed due to a\n"; OS << " // target predicate, that diagnostic is preferred.\n"; OS << " if (!HadMatchOtherThanPredicate &&\n"; - OS << " (it == MnemonicRange.first || ErrorInfo <= i" - << (HasMnemonicFirst ? "+1" : "") << ")) {\n"; - OS << " ErrorInfo = i" << (HasMnemonicFirst ? "+1" : "") << ";\n"; + OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n"; + OS << " ErrorInfo = ActualIdx;\n"; OS << " // InvalidOperand is the default. Prefer specificity.\n"; OS << " if (Diag != Match_InvalidOperand)\n"; OS << " RetCode = Diag;\n";