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Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140140 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2011-09-20 07:38:59 +00:00
parent 16ddc062c6
commit 3699261d3f
2 changed files with 71 additions and 3 deletions
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9
lib/Target/X86/X86ISelLowering.cpp
View File

@ -12567,9 +12567,12 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
// instructions match the semantics of the common C idiom x<y?x:y but not
// x<=y?x:y, because of how they handle negative zero (which can be
// ignored in unsafe-math mode).
if (Subtarget->hasXMMInt() && Cond.getOpcode() == ISD::SETCC &&
(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64 ||
LHS.getValueType() == MVT::v4f32 || LHS.getValueType() == MVT::v2f64)) {
if (Cond.getOpcode() == ISD::SETCC &&
((Subtarget->hasXMMInt() &&
(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::v4f32 ||
LHS.getValueType() == MVT::f64 || LHS.getValueType() == MVT::v2f64)) ||
(Subtarget->hasAVX() &&
(LHS.getValueType() == MVT::v8f32 || LHS.getValueType() == MVT::v4f64)))) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned Opcode = 0;

65
test/CodeGen/X86/avx-minmax.ll Normal file
View File

@ -0,0 +1,65 @@
; RUN: llc < %s -march=x86-64 -mattr=+avx -asm-verbose=false -join-physregs -enable-unsafe-fp-math -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=UNSAFE %s
; UNSAFE: maxpd:
; UNSAFE: vmaxpd %xmm
define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
%max_is_x = fcmp oge <2 x double> %x, %y
%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
ret <2 x double> %max
}
; UNSAFE: minpd:
; UNSAFE: vminpd %xmm
define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
%min_is_x = fcmp ole <2 x double> %x, %y
%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
ret <2 x double> %min
}
; UNSAFE: maxps:
; UNSAFE: vmaxps %xmm
define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
%max_is_x = fcmp oge <4 x float> %x, %y
%max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y
ret <4 x float> %max
}
; UNSAFE: minps:
; UNSAFE: vminps %xmm
define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
%min_is_x = fcmp ole <4 x float> %x, %y
%min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y
ret <4 x float> %min
}
; UNSAFE: vmaxpd:
; UNSAFE: vmaxpd %ymm
define <4 x double> @vmaxpd(<4 x double> %x, <4 x double> %y) {
%max_is_x = fcmp oge <4 x double> %x, %y
%max = select <4 x i1> %max_is_x, <4 x double> %x, <4 x double> %y
ret <4 x double> %max
}
; UNSAFE: vminpd:
; UNSAFE: vminpd %ymm
define <4 x double> @vminpd(<4 x double> %x, <4 x double> %y) {
%min_is_x = fcmp ole <4 x double> %x, %y
%min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y
ret <4 x double> %min
}
; UNSAFE: vmaxps:
; UNSAFE: vmaxps %ymm
define <8 x float> @vmaxps(<8 x float> %x, <8 x float> %y) {
%max_is_x = fcmp oge <8 x float> %x, %y
%max = select <8 x i1> %max_is_x, <8 x float> %x, <8 x float> %y
ret <8 x float> %max
}
; UNSAFE: vminps:
; UNSAFE: vminps %ymm
define <8 x float> @vminps(<8 x float> %x, <8 x float> %y) {
%min_is_x = fcmp ole <8 x float> %x, %y
%min = select <8 x i1> %min_is_x, <8 x float> %x, <8 x float> %y
ret <8 x float> %min
}