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Fix PR15950 A bug in DAG Combiner about undef mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181682 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9254,19 +9254,34 @@ static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
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for (unsigned I = 0; I != NumConcats; ++I) {
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// Make sure we're dealing with a copy.
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unsigned Begin = I * NumElemsPerConcat;
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if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
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return SDValue();
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for (unsigned J = 1; J != NumElemsPerConcat; ++J) {
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if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
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return SDValue();
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bool AllUndef = true, NoUndef = true;
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for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
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if (SVN->getMaskElt(J) >= 0)
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AllUndef = false;
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else
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NoUndef = false;
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}
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unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
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if (FirstElt < N0.getNumOperands())
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Ops.push_back(N0.getOperand(FirstElt));
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else
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Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
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if (NoUndef) {
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unsigned Begin = I * NumElemsPerConcat;
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if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
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return SDValue();
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for (unsigned J = 1; J != NumElemsPerConcat; ++J)
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if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
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return SDValue();
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unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
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if (FirstElt < N0.getNumOperands())
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Ops.push_back(N0.getOperand(FirstElt));
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else
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Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
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} else if (AllUndef) {
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Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
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} else { // Mixed with general masks and undefs, can't do optimization.
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return SDValue();
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}
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}
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return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, Ops.data(),
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10
test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll
Normal file
10
test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll
Normal file
@ -0,0 +1,10 @@
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; RUN: llc < %s
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target triple = "armv7-none-linux-gnueabi"
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define <3 x i64> @shuffle(i1 %dec1, i1 %dec0, <3 x i64> %b) {
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entry:
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%.sink = select i1 %dec1, <3 x i64> %b, <3 x i64> zeroinitializer
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%.sink15 = select i1 %dec0, <3 x i64> %b, <3 x i64> zeroinitializer
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%vecinit7 = shufflevector <3 x i64> %.sink, <3 x i64> %.sink15, <3 x i32> <i32 0, i32 4, i32 undef>
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ret <3 x i64> %vecinit7
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}
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