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This patch addresses a PPC64 ELF issue with passing parameters consisting of

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structs having size 3, 5, 6, or 7.  Such a struct must be passed and received
as right-justified within its register or memory slot.  The problem is only
present for structs that are passed in registers.

Previously, as part of a patch handling all structs of size less than 8, I
added logic to rotate the incoming register so that the struct was left-
justified prior to storing the whole register.  This was incorrect because
the address of the parameter had already been adjusted earlier to point to
the right-adjusted value in the storage slot.  Essentially I had accidentally
accounted for the right-adjustment twice.

In this patch, I removed the incorrect logic and reorganized the code to make
the flow clearer.

The removal of the rotates changes the expected code generation, so test case
structsinregs.ll has been modified to reflect this.  I also added a new test
case, jaggedstructs.ll, to demonstrate that structs of these sizes can now
be properly received and passed.

I've built and tested the code on powerpc64-unknown-linux-gnu with no new
regressions.  I also ran the GCC compatibility test suite and verified that
earlier problems with these structs are now resolved, with no new regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166680 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt 2012-10-25 13:38:09 +00:00
parent 6e8946c528
commit 37900c5dcb
3 changed files with 80 additions and 28 deletions
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50
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -2084,25 +2084,42 @@ PPCTargetLowering::LowerFormalArguments_64SVR4(
int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
InVals.push_back(FIN);
if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
if (ObjSize < 8) {
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg;
VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
EVT ObjType = (ObjSize == 1 ? MVT::i8 :
(ObjSize == 2 ? MVT::i16 : MVT::i32));
SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
MachinePointerInfo(FuncArg,
CurArgOffset),
ObjType, false, false, 0);
SDValue Store;
if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
EVT ObjType = (ObjSize == 1 ? MVT::i8 :
(ObjSize == 2 ? MVT::i16 : MVT::i32));
Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
MachinePointerInfo(FuncArg, CurArgOffset),
ObjType, false, false, 0);
} else {
// For sizes that don't fit a truncating store (3, 5, 6, 7),
// store the whole register as-is to the parameter save area
// slot. The address of the parameter was already calculated
// above (InVals.push_back(FIN)) to be the right-justified
// offset within the slot. For this store, we need a new
// frame index that points at the beginning of the slot.
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
MachinePointerInfo(FuncArg, ArgOffset),
false, false, 0);
}
MemOps.push_back(Store);
++GPR_idx;
}
// Whether we copied from a register or not, advance the offset
// into the parameter save area by a full doubleword.
ArgOffset += PtrByteSize;
continue;
}
for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
// Store whatever pieces of the object are in registers
// to memory. ArgOffset will be the address of the beginning
@ -2113,16 +2130,7 @@ PPCTargetLowering::LowerFormalArguments_64SVR4(
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
SDValue Shifted = Val;
// For 64-bit SVR4, small structs come in right-adjusted.
// Shift them left so the following logic works as expected.
if (ObjSize < 8) {
SDValue ShiftAmt = DAG.getConstant(64 - 8 * ObjSize, PtrVT);
Shifted = DAG.getNode(ISD::SHL, dl, PtrVT, Val, ShiftAmt);
}
SDValue Store = DAG.getStore(Val.getValue(1), dl, Shifted, FIN,
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
MachinePointerInfo(FuncArg, ArgOffset),
false, false, 0);
MemOps.push_back(Store);

48
test/CodeGen/PowerPC/jaggedstructs.ll Normal file
View File

@ -0,0 +1,48 @@
; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
; This tests receiving and re-passing parameters consisting of structures
; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in
; the parameter registers.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
%struct.S3 = type { [3 x i8] }
%struct.S5 = type { [5 x i8] }
%struct.S6 = type { [6 x i8] }
%struct.S7 = type { [7 x i8] }
define void @test(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7) nounwind {
entry:
call void @check(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7)
ret void
}
; CHECK: std 6, 216(1)
; CHECK: std 5, 208(1)
; CHECK: std 4, 200(1)
; CHECK: std 3, 192(1)
; CHECK: lbz {{[0-9]+}}, 199(1)
; CHECK: stb {{[0-9]+}}, 55(1)
; CHECK: lhz {{[0-9]+}}, 197(1)
; CHECK: sth {{[0-9]+}}, 53(1)
; CHECK: lbz {{[0-9]+}}, 207(1)
; CHECK: stb {{[0-9]+}}, 63(1)
; CHECK: lwz {{[0-9]+}}, 203(1)
; CHECK: stw {{[0-9]+}}, 59(1)
; CHECK: lhz {{[0-9]+}}, 214(1)
; CHECK: sth {{[0-9]+}}, 70(1)
; CHECK: lwz {{[0-9]+}}, 210(1)
; CHECK: stw {{[0-9]+}}, 66(1)
; CHECK: lbz {{[0-9]+}}, 223(1)
; CHECK: stb {{[0-9]+}}, 79(1)
; CHECK: lhz {{[0-9]+}}, 221(1)
; CHECK: sth {{[0-9]+}}, 77(1)
; CHECK: lwz {{[0-9]+}}, 217(1)
; CHECK: stw {{[0-9]+}}, 73(1)
; CHECK: ld 6, 72(1)
; CHECK: ld 5, 64(1)
; CHECK: ld 4, 56(1)
; CHECK: ld 3, 48(1)
declare void @check(%struct.S3* byval, %struct.S5* byval, %struct.S6* byval, %struct.S7* byval)

10
test/CodeGen/PowerPC/structsinregs.ll
View File

@ -188,17 +188,13 @@ entry:
%add13 = add nsw i32 %add11, %6
ret i32 %add13
; CHECK: sldi 9, 9, 8
; CHECK: sldi 8, 8, 16
; CHECK: sldi 7, 7, 24
; CHECK: sldi 5, 5, 40
; CHECK: stw 6, 76(1)
; CHECK: sth 4, 62(1)
; CHECK: stb 3, 55(1)
; CHECK: std 9, 96(1)
; CHECK: std 8, 88(1)
; CHECK: std 7, 80(1)
; CHECK: stw 6, 76(1)
; CHECK: std 5, 64(1)
; CHECK: sth 4, 62(1)
; CHECK: stb 3, 55(1)
; CHECK: lbz {{[0-9]+}}, 85(1)
; CHECK: lbz {{[0-9]+}}, 86(1)
; CHECK: lbz {{[0-9]+}}, 83(1)