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https://github.com/RPCS3/llvm.git
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Enable the shrink wrapping optimization for PPC64.
The changes in this patch are as follows:
1. Modify the emitPrologue and emitEpilogue methods to work properly when the prologue and epilogue blocks are not the first/last blocks in the function
2. Fix a bug in PPCEarlyReturn optimization caused by an empty entry block in the function
3. Override the runShrinkWrap PredicateFtor (defined in TargetMachine) to check whether shrink wrapping should run:
Shrink wrapping will run on PPC64 (Little Endian and Big Endian) unless -enable-shrink-wrap=false is specified on command line
A new test case, ppc-shrink-wrapping.ll was created based on the existing shrink wrapping tests for x86, arm, and arm64.
Phabricator review: http://reviews.llvm.org/D11817
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247237 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kit Barton
parent
b01975128c
commit
37d7ddff3e
@ -71,7 +71,14 @@ protected:
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for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
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PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
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bool OtherReference = false, BlockChanged = false;
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if ((*PI)->empty())
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continue;
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for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
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if (J == (*PI)->end())
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break;
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MachineInstrBuilder MIB;
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if (J->getOpcode() == PPC::B) {
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if (J->getOperand(0).getMBB() == &ReturnMBB) {
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@ -558,7 +558,6 @@ void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
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void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const PPCInstrInfo &TII =
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@ -590,7 +589,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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}
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}
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// Move MBBI back to the beginning of the function.
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// Move MBBI back to the beginning of the prologue block.
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MBBI = MBB.begin();
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// Work out frame sizes.
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@ -917,27 +916,18 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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}
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void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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assert(MBBI != MBB.end() && "Returning block has no terminator");
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
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DebugLoc dl;
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if (MBBI != MBB.end())
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dl = MBBI->getDebugLoc();
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const PPCInstrInfo &TII =
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*static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
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const PPCRegisterInfo *RegInfo =
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static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
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unsigned RetOpcode = MBBI->getOpcode();
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DebugLoc dl;
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assert((RetOpcode == PPC::BLR ||
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RetOpcode == PPC::BLR8 ||
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RetOpcode == PPC::TCRETURNri ||
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RetOpcode == PPC::TCRETURNdi ||
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RetOpcode == PPC::TCRETURNai ||
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RetOpcode == PPC::TCRETURNri8 ||
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RetOpcode == PPC::TCRETURNdi8 ||
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RetOpcode == PPC::TCRETURNai8) &&
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"Can only insert epilog into returning blocks");
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// Get alignment info so we know how to restore the SP.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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@ -1009,25 +999,30 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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PBPOffset = FFI->getObjectOffset(PBPIndex);
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}
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bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
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RetOpcode == PPC::TCRETURNdi ||
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RetOpcode == PPC::TCRETURNai ||
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RetOpcode == PPC::TCRETURNri8 ||
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RetOpcode == PPC::TCRETURNdi8 ||
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RetOpcode == PPC::TCRETURNai8;
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bool IsReturnBlock = MBBI->isReturn();
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if (IsReturnBlock) {
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unsigned RetOpcode = MBBI->getOpcode();
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bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
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RetOpcode == PPC::TCRETURNdi ||
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RetOpcode == PPC::TCRETURNai ||
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RetOpcode == PPC::TCRETURNri8 ||
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RetOpcode == PPC::TCRETURNdi8 ||
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RetOpcode == PPC::TCRETURNai8;
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if (UsesTCRet) {
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int MaxTCRetDelta = FI->getTailCallSPDelta();
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MachineOperand &StackAdjust = MBBI->getOperand(1);
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assert(StackAdjust.isImm() && "Expecting immediate value.");
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// Adjust stack pointer.
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int StackAdj = StackAdjust.getImm();
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int Delta = StackAdj - MaxTCRetDelta;
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assert((Delta >= 0) && "Delta must be positive");
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if (MaxTCRetDelta>0)
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FrameSize += (StackAdj +Delta);
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else
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FrameSize += StackAdj;
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if (UsesTCRet) {
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int MaxTCRetDelta = FI->getTailCallSPDelta();
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MachineOperand &StackAdjust = MBBI->getOperand(1);
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assert(StackAdjust.isImm() && "Expecting immediate value.");
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// Adjust stack pointer.
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int StackAdj = StackAdjust.getImm();
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int Delta = StackAdj - MaxTCRetDelta;
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assert((Delta >= 0) && "Delta must be positive");
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if (MaxTCRetDelta>0)
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FrameSize += (StackAdj +Delta);
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else
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FrameSize += StackAdj;
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}
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}
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// Frames of 32KB & larger require special handling because they cannot be
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@ -1110,52 +1105,55 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// Callee pop calling convention. Pop parameter/linkage area. Used for tail
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// call optimization
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if (MF.getTarget().Options.GuaranteedTailCallOpt &&
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(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
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MF.getFunction()->getCallingConv() == CallingConv::Fast) {
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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unsigned CallerAllocatedAmt = FI->getMinReservedArea();
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if (IsReturnBlock) {
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unsigned RetOpcode = MBBI->getOpcode();
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if (MF.getTarget().Options.GuaranteedTailCallOpt &&
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(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
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MF.getFunction()->getCallingConv() == CallingConv::Fast) {
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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unsigned CallerAllocatedAmt = FI->getMinReservedArea();
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if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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.addReg(SPReg).addImm(CallerAllocatedAmt);
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} else {
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BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
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if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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.addReg(SPReg).addImm(CallerAllocatedAmt);
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} else {
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BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
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.addImm(CallerAllocatedAmt >> 16);
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BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
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BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
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.addReg(ScratchReg, RegState::Kill)
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.addImm(CallerAllocatedAmt & 0xFFFF);
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BuildMI(MBB, MBBI, dl, AddInst)
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BuildMI(MBB, MBBI, dl, AddInst)
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.addReg(SPReg)
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.addReg(FPReg)
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.addReg(ScratchReg);
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}
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} else if (RetOpcode == PPC::TCRETURNdi) {
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MBBI = MBB.getLastNonDebugInstr();
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
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} else if (RetOpcode == PPC::TCRETURNri) {
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MBBI = MBB.getLastNonDebugInstr();
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assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
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} else if (RetOpcode == PPC::TCRETURNai) {
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MBBI = MBB.getLastNonDebugInstr();
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
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} else if (RetOpcode == PPC::TCRETURNdi8) {
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MBBI = MBB.getLastNonDebugInstr();
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
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} else if (RetOpcode == PPC::TCRETURNri8) {
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MBBI = MBB.getLastNonDebugInstr();
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assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
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} else if (RetOpcode == PPC::TCRETURNai8) {
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MBBI = MBB.getLastNonDebugInstr();
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
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}
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} else if (RetOpcode == PPC::TCRETURNdi) {
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MBBI = MBB.getLastNonDebugInstr();
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
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} else if (RetOpcode == PPC::TCRETURNri) {
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MBBI = MBB.getLastNonDebugInstr();
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assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
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} else if (RetOpcode == PPC::TCRETURNai) {
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MBBI = MBB.getLastNonDebugInstr();
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
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} else if (RetOpcode == PPC::TCRETURNdi8) {
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MBBI = MBB.getLastNonDebugInstr();
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
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} else if (RetOpcode == PPC::TCRETURNri8) {
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MBBI = MBB.getLastNonDebugInstr();
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assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
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} else if (RetOpcode == PPC::TCRETURNai8) {
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MBBI = MBB.getLastNonDebugInstr();
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
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}
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}
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}
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@ -1710,3 +1708,8 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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return true;
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}
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bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
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return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
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MF.getSubtarget<PPCSubtarget>().isPPC64());
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}
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@ -92,6 +92,8 @@ public:
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const SpillSlot *
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getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
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bool enableShrinkWrapping(const MachineFunction &MF) const override;
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};
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} // End llvm namespace
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556
test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
Normal file
556
test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
Normal file
@ -0,0 +1,556 @@
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
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;
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; Note: Lots of tests use inline asm instead of regular calls.
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; This allows to have a better control on what the allocation will do.
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; Otherwise, we may have spill right in the entry block, defeating
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; shrink-wrapping. Moreover, some of the inline asm statement (nop)
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; are here to ensure that the related paths do not end up as critical
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; edges.
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; Initial motivating example: Simple diamond with a call just on one side.
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; CHECK-LABEL: foo:
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;
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; Compare the arguments and return
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; No prologue needed.
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; ENABLE: cmpw 0, 3, 4
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; ENABLE-NEXT: bgelr 0
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;
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; Prologue code.
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; At a minimum, we save/restore the link register. Other registers may be saved
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; as well.
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; CHECK: mflr
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;
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; Compare the arguments and jump to exit.
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; After the prologue is set.
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; DISABLE: cmpw 0, 3, 4
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; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]]
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;
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; Store %a on the stack
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; CHECK: stw 3, {{[0-9]+([0-9]+)}}
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; Set the alloca address in the second argument.
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; CHECK-NEXT: addi 4, 1, {{[0-9]+}}
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; Set the first argument to zero.
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: bl doSomething
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;
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; With shrink-wrapping, epilogue is just after the call.
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; Restore the link register and return.
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; Note that there could be other epilog code before the link register is
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; restored but we will not check for it here.
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; ENABLE: mtlr
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; ENABLE-NEXT: blr
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;
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; DISABLE: [[EXIT_LABEL]]:
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;
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; Without shrink-wrapping, epilogue is in the exit block.
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; Epilogue code. (What we pop does not matter.)
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; DISABLE: mtlr 0
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; DISABLE-NEXT: blr
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;
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define i32 @foo(i32 %a, i32 %b) {
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%tmp = alloca i32, align 4
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%tmp2 = icmp slt i32 %a, %b
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br i1 %tmp2, label %true, label %false
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true:
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store i32 %a, i32* %tmp, align 4
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%tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
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br label %false
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false:
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%tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
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ret i32 %tmp.0
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}
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; Function Attrs: optsize
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declare i32 @doSomething(i32, i32*)
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; Check that we do not perform the restore inside the loop whereas the save
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; is outside.
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; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
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;
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; Shrink-wrapping allows to skip the prologue in the else case.
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; ENABLE: cmplwi 0, 3, 0
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; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the link register
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; CHECK: mflr 0
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;
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; DISABLE: cmplwi 0, 3, 0
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; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Loop preheader
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; CHECK-DAG: li [[SUM:[0-9]+]], 0
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; CHECK-DAG: li [[IV:[0-9]+]], 10
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;
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; Loop body
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; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
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; CHECK: bl something
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; CHECK-DAG: addi [[IV]], [[IV]], -1
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; CHECK-DAG: add [[SUM]], 3, [[SUM]]
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; CHECK-NEXT: cmplwi [[IV]], 0
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; CHECK-NEXT: bne 0, .[[LOOP]]
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;
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; Next BB.
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; CHECK: slwi 3, [[SUM]], 3
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;
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; Jump to epilogue.
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; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
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;
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; DISABLE: .[[ELSE_LABEL]]: # %if.else
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; Shift second argument by one and store into returned register.
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; DISABLE: slwi 3, 4, 1
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; DISABLE: .[[EPILOG_BB]]: # %if.end
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;
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; Epilogue code.
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; CHECK: mtlr 0
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; CHECK-NEXT: blr
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;
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; ENABLE: .[[ELSE_LABEL]]: # %if.else
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; Shift second argument by one and store into returned register.
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; ENABLE: slwi 3, 4, 1
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; ENABLE-NEXT: blr
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define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
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%sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
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%call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
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%add = add nsw i32 %call, %sum.04
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%inc = add nuw nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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%shl = shl i32 %add, 3
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %if.else, %for.end
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%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
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ret i32 %sum.1
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}
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declare i32 @something(...)
|
||||
|
||||
; Check that we do not perform the shrink-wrapping inside the loop even
|
||||
; though that would be legal. The cost model must prevent that.
|
||||
; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
|
||||
; Prologue code.
|
||||
; Make sure we save the link register before the call
|
||||
; CHECK: mflr 0
|
||||
;
|
||||
; Loop preheader
|
||||
; CHECK-DAG: li [[SUM:[0-9]+]], 0
|
||||
; CHECK-DAG: li [[IV:[0-9]+]], 10
|
||||
;
|
||||
; Loop body
|
||||
; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
|
||||
; CHECK: bl something
|
||||
; CHECK-DAG: addi [[IV]], [[IV]], -1
|
||||
; CHECK-DAG: add [[SUM]], 3, [[SUM]]
|
||||
; CHECK-NEXT: cmplwi [[IV]], 0
|
||||
; CHECK-NEXT: bne 0, .[[LOOP]]
|
||||
;
|
||||
; Next BB
|
||||
; CHECK: %for.exit
|
||||
; CHECK: mtlr 0
|
||||
; CHECK-NEXT: blr
|
||||
define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
|
||||
entry:
|
||||
br label %for.preheader
|
||||
|
||||
for.preheader:
|
||||
tail call void asm "nop", ""()
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %for.body, %entry
|
||||
%i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ]
|
||||
%sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ]
|
||||
%call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
|
||||
%add = add nsw i32 %call, %sum.03
|
||||
%inc = add nuw nsw i32 %i.04, 1
|
||||
%exitcond = icmp eq i32 %inc, 10
|
||||
br i1 %exitcond, label %for.exit, label %for.body
|
||||
|
||||
for.exit:
|
||||
tail call void asm "nop", ""()
|
||||
br label %for.end
|
||||
|
||||
for.end: ; preds = %for.body
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
|
||||
; Check with a more complex case that we do not have save within the loop and
|
||||
; restore outside.
|
||||
; CHECK-LABEL: loopInfoSaveOutsideLoop:
|
||||
;
|
||||
; ENABLE: cmplwi 0, 3, 0
|
||||
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Prologue code.
|
||||
; Make sure we save the link register
|
||||
; CHECK: mflr 0
|
||||
;
|
||||
; DISABLE: cmplwi 0, 3, 0
|
||||
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Loop preheader
|
||||
; CHECK-DAG: li [[SUM:[0-9]+]], 0
|
||||
; CHECK-DAG: li [[IV:[0-9]+]], 10
|
||||
;
|
||||
; Loop body
|
||||
; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
|
||||
; CHECK: bl something
|
||||
; CHECK-DAG: addi [[IV]], [[IV]], -1
|
||||
; CHECK-DAG: add [[SUM]], 3, [[SUM]]
|
||||
; CHECK-NEXT: cmplwi [[IV]], 0
|
||||
; CHECK-NEXT: bne 0, .[[LOOP]]
|
||||
;
|
||||
; Next BB
|
||||
; CHECK: bl somethingElse
|
||||
; CHECK: slwi 3, [[SUM]], 3
|
||||
;
|
||||
; Jump to epilogue
|
||||
; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
|
||||
;
|
||||
; DISABLE: .[[ELSE_LABEL]]: # %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; DISABLE: slwi 3, 4, 1
|
||||
;
|
||||
; DISABLE: .[[EPILOG_BB]]: # %if.end
|
||||
; Epilog code
|
||||
; CHECK: mtlr 0
|
||||
; CHECK-NEXT: blr
|
||||
;
|
||||
; ENABLE: .[[ELSE_LABEL]]: # %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; ENABLE: slwi 3, 4, 1
|
||||
; ENABLE-NEXT: blr
|
||||
define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %for.preheader
|
||||
|
||||
for.preheader:
|
||||
tail call void asm "nop", ""()
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
|
||||
%sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
|
||||
%call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
|
||||
%add = add nsw i32 %call, %sum.04
|
||||
%inc = add nuw nsw i32 %i.05, 1
|
||||
%exitcond = icmp eq i32 %inc, 10
|
||||
br i1 %exitcond, label %for.end, label %for.body
|
||||
|
||||
for.end: ; preds = %for.body
|
||||
tail call void bitcast (void (...)* @somethingElse to void ()*)()
|
||||
%shl = shl i32 %add, 3
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%mul = shl nsw i32 %N, 1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %for.end
|
||||
%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
|
||||
ret i32 %sum.1
|
||||
}
|
||||
|
||||
declare void @somethingElse(...)
|
||||
|
||||
; Check with a more complex case that we do not have restore within the loop and
|
||||
; save outside.
|
||||
; CHECK-LABEL: loopInfoRestoreOutsideLoop:
|
||||
;
|
||||
; ENABLE: cmplwi 0, 3, 0
|
||||
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Prologue code.
|
||||
; Make sure we save the link register
|
||||
; CHECK: mflr 0
|
||||
;
|
||||
; DISABLE: cmplwi 0, 3, 0
|
||||
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; CHECK: bl somethingElse
|
||||
;
|
||||
; Loop preheader
|
||||
; CHECK-DAG: li [[SUM:[0-9]+]], 0
|
||||
; CHECK-DAG: li [[IV:[0-9]+]], 10
|
||||
;
|
||||
; Loop body
|
||||
; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
|
||||
; CHECK: bl something
|
||||
; CHECK-DAG: addi [[IV]], [[IV]], -1
|
||||
; CHECK-DAG: add [[SUM]], 3, [[SUM]]
|
||||
; CHECK-NEXT: cmplwi [[IV]], 0
|
||||
; CHECK-NEXT: bne 0, .[[LOOP]]
|
||||
;
|
||||
; Next BB.
|
||||
; slwi 3, [[SUM]], 3
|
||||
;
|
||||
; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
|
||||
;
|
||||
; DISABLE: .[[ELSE_LABEL]]: # %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; DISABLE: slwi 3, 4, 1
|
||||
; DISABLE: .[[EPILOG_BB]]: # %if.end
|
||||
;
|
||||
; Epilogue code.
|
||||
; CHECK: mtlr 0
|
||||
; CHECK-NEXT: blr
|
||||
;
|
||||
; ENABLE: .[[ELSE_LABEL]]: # %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; ENABLE: slwi 3, 4, 1
|
||||
; ENABLE-NEXT: blr
|
||||
define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void bitcast (void (...)* @somethingElse to void ()*)()
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %for.body, %if.then
|
||||
%i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ]
|
||||
%sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
|
||||
%call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
|
||||
%add = add nsw i32 %call, %sum.04
|
||||
%inc = add nuw nsw i32 %i.05, 1
|
||||
%exitcond = icmp eq i32 %inc, 10
|
||||
br i1 %exitcond, label %for.end, label %for.body
|
||||
|
||||
for.end: ; preds = %for.body
|
||||
%shl = shl i32 %add, 3
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%mul = shl nsw i32 %N, 1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %for.end
|
||||
%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
|
||||
ret i32 %sum.1
|
||||
}
|
||||
|
||||
; Check that we handle function with no frame information correctly.
|
||||
; CHECK-LABEL: emptyFrame:
|
||||
; CHECK: # %entry
|
||||
; CHECK-NEXT: li 3, 0
|
||||
; CHECK-NEXT: blr
|
||||
define i32 @emptyFrame() {
|
||||
entry:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
|
||||
; Check that we handle inline asm correctly.
|
||||
; CHECK-LABEL: inlineAsm:
|
||||
;
|
||||
; ENABLE: cmplwi 0, 3, 0
|
||||
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Prologue code.
|
||||
; Make sure we save the CSR used in the inline asm: r14
|
||||
; ENABLE-DAG: li [[IV:[0-9]+]], 10
|
||||
; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
|
||||
;
|
||||
; DISABLE: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
|
||||
; DISABLE: cmplwi 0, 3, 0
|
||||
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
|
||||
; DISABLE: li [[IV:[0-9]+]], 10
|
||||
;
|
||||
; CHECK: nop
|
||||
; CHECK: mtctr [[IV]]
|
||||
;
|
||||
; CHECK: .[[LOOP_LABEL:LBB[0-9_]+]]: # %for.body
|
||||
; Inline asm statement.
|
||||
; CHECK: addi 14, 14, 1
|
||||
; CHECK: bdnz .[[LOOP_LABEL]]
|
||||
;
|
||||
; Epilogue code.
|
||||
; CHECK: li 3, 0
|
||||
; CHECK-DAG: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
|
||||
; CHECK: nop
|
||||
; CHECK: blr
|
||||
;
|
||||
; CHECK: [[ELSE_LABEL]]
|
||||
; CHECK-NEXT: slwi 3, 4, 1
|
||||
; DISABLE: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
|
||||
; CHECK-NEXT blr
|
||||
;
|
||||
define i32 @inlineAsm(i32 %cond, i32 %N) {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %for.preheader
|
||||
|
||||
for.preheader:
|
||||
tail call void asm "nop", ""()
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
%i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
|
||||
tail call void asm "addi 14, 14, 1", "~{r14}"()
|
||||
%inc = add nuw nsw i32 %i.03, 1
|
||||
%exitcond = icmp eq i32 %inc, 10
|
||||
br i1 %exitcond, label %for.exit, label %for.body
|
||||
|
||||
for.exit:
|
||||
tail call void asm "nop", ""()
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%mul = shl nsw i32 %N, 1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %for.body, %if.else
|
||||
%sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
|
||||
ret i32 %sum.0
|
||||
}
|
||||
|
||||
|
||||
; Check that we handle calls to variadic functions correctly.
|
||||
; CHECK-LABEL: callVariadicFunc:
|
||||
;
|
||||
; ENABLE: cmplwi 0, 3, 0
|
||||
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Prologue code.
|
||||
; CHECK: mflr 0
|
||||
;
|
||||
; DISABLE: cmplwi 0, 3, 0
|
||||
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Setup of the varags.
|
||||
; CHECK: mr 4, 3
|
||||
; CHECK-NEXT: mr 5, 3
|
||||
; CHECK-NEXT: mr 6, 3
|
||||
; CHECK-NEXT: mr 7, 3
|
||||
; CHECK-NEXT: mr 8, 3
|
||||
; CHECK-NEXT: mr 9, 3
|
||||
; CHECK-NEXT: bl someVariadicFunc
|
||||
; CHECK: slwi 3, 3, 3
|
||||
; DISABLE: b .[[EPILOGUE_BB:LBB[0-9_]+]]
|
||||
;
|
||||
; ENABLE: mtlr 0
|
||||
; ENABLE-NEXT: blr
|
||||
;
|
||||
; CHECK: .[[ELSE_LABEL]]: # %if.else
|
||||
; CHECK-NEXT: slwi 3, 4, 1
|
||||
;
|
||||
; DISABLE: .[[EPILOGUE_BB]]: # %if.end
|
||||
; DISABLE: mtlr
|
||||
; CHECK: blr
|
||||
define i32 @callVariadicFunc(i32 %cond, i32 %N) {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
|
||||
%shl = shl i32 %call, 3
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%mul = shl nsw i32 %N, 1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ]
|
||||
ret i32 %sum.0
|
||||
}
|
||||
|
||||
declare i32 @someVariadicFunc(i32, ...)
|
||||
|
||||
|
||||
|
||||
; Make sure we do not insert unreachable code after noreturn function.
|
||||
; Although this is not incorrect to insert such code, it is useless
|
||||
; and it hurts the binary size.
|
||||
;
|
||||
; CHECK-LABEL: noreturn:
|
||||
; DISABLE: mflr 0
|
||||
;
|
||||
; CHECK: cmplwi 3, 0
|
||||
; CHECK-NEXT: bne 0, .[[ABORT:LBB[0-9_]+]]
|
||||
;
|
||||
; CHECK: li 3, 42
|
||||
;
|
||||
; DISABLE: mtlr 0
|
||||
;
|
||||
; CHECK-NEXT: blr
|
||||
;
|
||||
; CHECK: .[[ABORT]]: # %if.abort
|
||||
;
|
||||
; ENABLE: mflr 0
|
||||
;
|
||||
; CHECK: bl abort
|
||||
; ENABLE-NOT: mtlr 0
|
||||
define i32 @noreturn(i8 signext %bad_thing) {
|
||||
entry:
|
||||
%tobool = icmp eq i8 %bad_thing, 0
|
||||
br i1 %tobool, label %if.end, label %if.abort
|
||||
|
||||
if.abort:
|
||||
tail call void @abort() #0
|
||||
unreachable
|
||||
|
||||
if.end:
|
||||
ret i32 42
|
||||
}
|
||||
|
||||
declare void @abort() #0
|
||||
|
||||
attributes #0 = { noreturn nounwind }
|
||||
|
||||
|
||||
; Make sure that we handle infinite loops properly When checking that the Save
|
||||
; and Restore blocks are control flow equivalent, the loop searches for the
|
||||
; immediate (post) dominator for the (restore) save blocks. When either the Save
|
||||
; or Restore block is located in an infinite loop the only immediate (post)
|
||||
; dominator is itself. In this case, we cannot perform shrink wrapping, but we
|
||||
; should return gracefully and continue compilation.
|
||||
; The only condition for this test is the compilation finishes correctly.
|
||||
;
|
||||
; CHECK-LABEL: infiniteloop
|
||||
; CHECK: blr
|
||||
define void @infiniteloop() {
|
||||
entry:
|
||||
br i1 undef, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
%ptr = alloca i32, i32 4
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %for.body, %entry
|
||||
%sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
|
||||
%call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
|
||||
%add = add nsw i32 %call, %sum.03
|
||||
store i32 %add, i32* %ptr
|
||||
br label %for.body
|
||||
|
||||
if.end:
|
||||
ret void
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user