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R600: Allow ftrunc
v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc v3: move ftrunc pattern next to TRUNC definition, it's available since R600 Patch By: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197783 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -60,6 +60,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FRINT, MVT::f32, Legal);
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setOperationAction(ISD::FROUND, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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// The hardware supports ROTR, but not ROTL
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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@ -184,6 +185,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FADD, VT, Expand);
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setOperationAction(ISD::FDIV, VT, Expand);
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setOperationAction(ISD::FFLOOR, VT, Expand);
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setOperationAction(ISD::FTRUNC, VT, Expand);
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setOperationAction(ISD::FMUL, VT, Expand);
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setOperationAction(ISD::FRINT, VT, Expand);
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setOperationAction(ISD::FSQRT, VT, Expand);
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@ -733,6 +733,9 @@ def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
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def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
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def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
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// Add also ftrunc intrinsic pattern
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def : Pat<(ftrunc f32:$src0), (TRUNC $src0)>;
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def MOV : R600_1OP <0x19, "MOV", []>;
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let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
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13
test/CodeGen/R600/llvm.trunc.ll
Normal file
13
test/CodeGen/R600/llvm.trunc.ll
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@ -0,0 +1,13 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK-LABEL: @trunc_f32
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; CHECK: TRUNC
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define void @trunc_f32(float addrspace(1)* %out, float %in) {
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entry:
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%0 = call float @llvm.trunc.f32(float %in)
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store float %0, float addrspace(1)* %out
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ret void
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}
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declare float @llvm.trunc.f32(float)
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