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[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
To make ISD::VSELECT available(legal) so long as there are altivec instruction, otherwise it's default behavior is expanding, which is legalized at type-legalization phase. Use xxsel to match vselect if vsx is open, or use vsel. Differential Revision: https://reviews.llvm.org/D49531 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346824 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zi Xuan Wu
parent
7215ab82d4
commit
382877c17c
@ -4736,14 +4736,6 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
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CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
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return;
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}
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case ISD::VSELECT:
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if (PPCSubTarget->hasVSX()) {
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SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
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CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
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return;
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}
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break;
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case ISD::VECTOR_SHUFFLE:
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if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
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N->getValueType(0) == MVT::v2i64)) {
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@ -586,6 +586,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
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setOperationAction(ISD::SELECT, VT, Promote);
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AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
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setOperationAction(ISD::VSELECT, VT, Legal);
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setOperationAction(ISD::SELECT_CC, VT, Promote);
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AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
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setOperationAction(ISD::STORE, VT, Promote);
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@ -626,7 +627,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
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setOperationAction(ISD::FPOW, VT, Expand);
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setOperationAction(ISD::BSWAP, VT, Expand);
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setOperationAction(ISD::VSELECT, VT, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
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setOperationAction(ISD::ROTL, VT, Expand);
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setOperationAction(ISD::ROTR, VT, Expand);
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@ -727,12 +727,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
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setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
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setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
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setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
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setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
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setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
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setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
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// Share the Altivec comparison restrictions.
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setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
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setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
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@ -1051,6 +1051,20 @@ def : Pat<(v4f32 (ftrunc v4f32:$vA)),
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def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
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(VRFIN $vA)>;
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// Vector selection
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def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
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(VSEL $vC, $vB, $vA)>;
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def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
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(VSEL $vC, $vB, $vA)>;
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def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)),
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(VSEL $vC, $vB, $vA)>;
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def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)),
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(VSEL $vC, $vB, $vA)>;
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def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)),
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(VSEL $vC, $vB, $vA)>;
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def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)),
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(VSEL $vC, $vB, $vA)>;
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} // end HasAltivec
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def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
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@ -1152,6 +1152,26 @@ def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
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def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
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(XVRSQRTEDP $A)>;
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// Vector selection
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def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
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(COPY_TO_REGCLASS
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(XXSEL (COPY_TO_REGCLASS $vC, VSRC),
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(COPY_TO_REGCLASS $vB, VSRC),
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(COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
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def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
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(COPY_TO_REGCLASS
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(XXSEL (COPY_TO_REGCLASS $vC, VSRC),
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(COPY_TO_REGCLASS $vB, VSRC),
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(COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
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def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC),
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(XXSEL $vC, $vB, $vA)>;
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def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC),
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(XXSEL $vC, $vB, $vA)>;
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def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),
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(XXSEL $vC, $vB, $vA)>;
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def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),
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(XXSEL $vC, $vB, $vA)>;
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let Predicates = [IsLittleEndian] in {
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def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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@ -1,7 +1,100 @@
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-linux-gnu -mattr=+altivec | FileCheck %s
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
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; CHECK: vsel_float
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
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entry:
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%m = fcmp oeq <4 x float> %c, %d
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%v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
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ret <4 x float> %v
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}
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; CHECK-VSX-LABLE: test1
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; CHECK-VSX: xvcmpeqsp [[REG1:(vs|v)[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test1
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; CHECK-NOVSX: vcmpeqfp v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
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entry:
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%m = fcmp oeq <2 x double> %c, %d
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%v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
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ret <2 x double> %v
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}
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; CHECK-VSX-LABLE: test2
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; CHECK-VSX: xvcmpeqdp [[REG1:(vs|v)[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test2
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; CHECK-NOVSX: fcmp
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; CHECK-NOVSX: fcmp
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; CHECK-NOVSX: blr
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define <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
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entry:
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%m = icmp eq <16 x i8> %c, %d
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%v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %v
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}
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; CHECK-VSX-LABLE: test3
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; CHECK-VSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test3
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; CHECK-NOVSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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define <8 x i16> @test4(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
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entry:
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%m = icmp eq <8 x i16> %c, %d
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%v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %v
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}
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; CHECK-VSX-LABLE: test4
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; CHECK-VSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test4
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; CHECK-NOVSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
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entry:
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%m = icmp eq <4 x i32> %c, %d
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%v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %v
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}
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; CHECK-VSX-LABLE: test5
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; CHECK-VSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test5
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; CHECK-NOVSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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define <2 x i64> @test6(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
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entry:
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%m = icmp eq <2 x i64> %c, %d
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%v = select <2 x i1> %m, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %v
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}
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; CHECK-VSX-LABLE: test6
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; CHECK-VSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test6
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; CHECK-NOVSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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