RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-04-03 13:51:39 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Do not promote i32 arguments to i64. This was causing unnecessary sign extension

Browse Source 
instructions to be emitted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-02-17 02:20:26 +00:00
parent 3106b8b18b
commit 38bdc5762f
2 changed files with 16 additions and 14 deletions

25
lib/Target/Mips/MipsCallingConv.td

@ -38,10 +38,15 @@ def CC_MipsN : CallingConv<[
// Handles byval parameters.
CCIfByVal<CCCustom<"CC_Mips64Byval">>,
// Promote i8/i16/i32 arguments to i64.
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// Promote i8/i16 arguments to i32.
CCIfType<[i8, i16], CCPromoteToType<i32>>,
// Integer arguments are passed in integer registers.
CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
T0, T1, T2, T3],
[F12, F13, F14, F15,
F16, F17, F18, F19]>>,
CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
T0_64, T1_64, T2_64, T3_64],
[D12_64, D13_64, D14_64, D15_64,
@ -60,8 +65,8 @@ def CC_MipsN : CallingConv<[
T0_64, T1_64, T2_64, T3_64]>>,
// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
CCIfType<[i64, f64], CCAssignToStack<8, 8>>,
CCIfType<[f32], CCAssignToStack<4, 8>>
CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
CCIfType<[i64, f64], CCAssignToStack<8, 8>>
]>;
// N32/64 variable arguments.
@ -70,17 +75,17 @@ def CC_MipsN_VarArg : CallingConv<[
// Handles byval parameters.
CCIfByVal<CCCustom<"CC_Mips64Byval">>,
// Promote i8/i16/i32 arguments to i64.
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// Promote i8/i16 arguments to i32.
CCIfType<[i8, i16], CCPromoteToType<i32>>,
CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
T0_64, T1_64, T2_64, T3_64]>>,
CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
CCIfType<[i64, f64], CCAssignToStack<8, 8>>,
CCIfType<[f32], CCAssignToStack<4, 8>>
CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
CCIfType<[i64, f64], CCAssignToStack<8, 8>>
]>;
def RetCC_MipsN : CallingConv<[

5
lib/Target/Mips/MipsISelLowering.cpp

@ -2299,10 +2299,7 @@ MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
break;
case CCValAssign::AExt:
if (ValVT == MVT::i32)
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
else
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
break;
}