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Added a new register class for segment registers

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to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan 2009-09-15 18:47:29 +00:00
parent 7d1a7c0417
commit 38fee0edcf
3 changed files with 25 additions and 0 deletions
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10
lib/Target/X86/X86Instr64bit.td
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@ -330,6 +330,16 @@ def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
"mov{q}\t{%rax, $dst|$dst, %rax}", []>;
// Moves to and from segment registers
def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>;
def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>;
def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>;
def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>;
// Sign/Zero extenders
// MOVSX64rr8 always has a REX prefix and it has an 8-bit register

10
lib/Target/X86/X86InstrInfo.td
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@ -946,6 +946,16 @@ def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs i16imm:$dst), (ins),
def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs i32imm:$dst), (ins),
"mov{l}\t{%eax, $dst|$dst, %eax}", []>;
// Moves to and from segment registers
def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>;
def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>;
def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>;
def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>;
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
"mov{b}\t{$src, $dst|$dst, $src}",

5
lib/Target/X86/X86RegisterInfo.td
View File

@ -440,6 +440,11 @@ def GR64 : RegisterClass<"X86", [i64], 64,
}];
}
// Segment registers for use by MOV instructions (and others) that have a
// segment register as one operand. Always contain a 16-bit segment
// descriptor.
def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> {
}
// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"