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Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170671 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
bacbf1c2cb
commit
39498d1ff0
@ -59,9 +59,6 @@ class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
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bits<6> imm6;
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}
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class Immext<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX> {
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let isCodeGenOnly = 1;
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bits<26> imm26;
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}
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let isCodeGenOnly = 1 in
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class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX>;
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@ -12,10 +12,14 @@
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//===----------------------------------------------------------------------===//
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let neverHasSideEffects = 1 in
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def IMMEXT : Immext<(outs), (ins),
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"/* immext #... */",
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[]>,
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Requires<[HasV4T]>;
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class T_Immext<dag ins> :
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EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
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Requires<[HasV4T]>;
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def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
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def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
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def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
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def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
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// Hexagon V4 Architecture spec defines 8 instruction classes:
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// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
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@ -83,86 +87,77 @@ def IMMEXT : Immext<(outs), (ins),
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// Shift halfword.
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let isPredicated = 1 in
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let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
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def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = aslh($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = aslh($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = aslh($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = aslh($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = asrh($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = asrh($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = asrh($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = asrh($src2)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Sign extend.
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let isPredicated = 1 in
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let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
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def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = sxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = sxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = sxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = sxtb($src2)",
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@ -170,94 +165,86 @@ def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = sxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = sxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = sxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = sxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Zero exten.
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let neverHasSideEffects = 1, isPredicated = 1 in
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let neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in {
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def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = zxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = zxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = zxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = zxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = zxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = zxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = zxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = zxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Generate frame index addresses.
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let neverHasSideEffects = 1, isReMaterializable = 1 in
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let neverHasSideEffects = 1, isReMaterializable = 1,
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isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
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def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s32Imm:$offset),
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"$dst = add($src1, ##$offset)",
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@ -241,8 +241,9 @@ static bool IsIndirectCall(MachineInstr* MI) {
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// reservation fail.
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void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
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const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
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MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
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QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
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MachineFunction *MF = MI->getParent()->getParent();
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MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
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MI->getDebugLoc());
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if (ResourceTracker->canReserveResources(PseudoMI)) {
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ResourceTracker->reserveResources(PseudoMI);
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@ -259,7 +260,7 @@ bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
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assert(QII->isExtended(MI) &&
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"Should only be called for constant extended instructions");
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MachineFunction *MF = MI->getParent()->getParent();
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MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT),
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MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
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MI->getDebugLoc());
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bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
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MF->DeleteMachineInstr(PseudoMI);
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@ -270,8 +271,9 @@ bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
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// true, otherwise, return false.
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bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
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const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
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MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
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QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
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MachineFunction *MF = MI->getParent()->getParent();
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MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
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MI->getDebugLoc());
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if (ResourceTracker->canReserveResources(PseudoMI)) {
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ResourceTracker->reserveResources(PseudoMI);
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