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[mips] Preparatory work for a generic scheduler
Extend instruction definitions from nearly all ISAs to include appropriate instruction itineraries. Change MIPS16s gp prologue generation to use real instructions instead of using a pseudo instruction. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23548 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279623 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis
parent
e01c44e124
commit
39b3d8a9d4
@ -301,6 +301,7 @@ class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
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list<Register> Defs = [AT];
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InstrItinClass Itinerary = II_BCCZC;
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}
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class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
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@ -348,6 +349,7 @@ class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
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list<Register> Defs = [AT];
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InstrItinClass Itinerary = II_BCCC;
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}
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class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
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@ -363,27 +365,28 @@ class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
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class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
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GPR32Opnd>;
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class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
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class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
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class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
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class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
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class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
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class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
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class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
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class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
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class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
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class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
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class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
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: BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
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dag InOperandList = (ins opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$offset");
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bit isBarrier = 1;
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InstrItinClass Itinerary = Itin;
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}
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class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> {
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class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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}
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class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm>;
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class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC>;
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class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
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!strconcat("bc16", "\t$offset"), [],
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@ -407,8 +410,8 @@ class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
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class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
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class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
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class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
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class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
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class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
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class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
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class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm> {
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@ -416,6 +419,7 @@ class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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dag InOperandList = (ins GPROpnd:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_BITSWAP;
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}
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class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
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@ -423,63 +427,74 @@ class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
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class BRK_MMR6_DESC : BRK_FT<"break">;
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class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
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RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
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RegisterOperand GPROpnd, InstrItinClass Itin>
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: MMR6Arch<instr_asm> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
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string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeCacheOpMM";
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InstrItinClass Itinerary = Itin;
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}
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class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
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class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
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class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,
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II_CACHE>;
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class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,
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II_PREF>;
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class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
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RegisterOperand GPROpnd> :
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CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
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GPROpnd> {
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RegisterOperand GPROpnd, InstrItinClass Itin>
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: CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, GPROpnd, Itin> {
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string DecoderMethod = "DecodePrefeOpMM";
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}
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class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
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class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
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class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9,
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GPR32Opnd, II_PREFE>;
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class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9,
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GPR32Opnd, II_CACHEE>;
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class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
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RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
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RegisterOperand GPROpnd, InstrItinClass Itin>
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: MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins MemOpnd:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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string DecoderMethod = "DecodeLoadByte15";
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bit mayLoad = 1;
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InstrItinClass Itinerary = Itin;
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}
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class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>;
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class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>;
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class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
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class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
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II_LBU>;
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class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
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RegisterOperand GPROpnd>
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: LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> {
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RegisterOperand GPROpnd, InstrItinClass Itin>
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: LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd, Itin> {
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let DecoderMethod = "DecodeLoadByte9";
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}
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class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>;
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class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>;
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class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd,
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II_LBE>;
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class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd,
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II_LBUE>;
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class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm> {
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class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass Itin> : MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins GPROpnd:$rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
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InstrItinClass Itinerary = Itin;
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}
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class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
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class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
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class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
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class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
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class EHB_MMR6_DESC : Barrier<"ehb">;
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class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
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class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd>;
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class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
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class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
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class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
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class ERET_MMR6_DESC : ER_FT<"eret">;
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class DERET_MMR6_DESC : ER_FT<"deret">;
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class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
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class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
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class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
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class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
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class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
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: MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
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@ -492,23 +507,25 @@ class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
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class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
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class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
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RegisterOperand GPROpnd>
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RegisterOperand GPROpnd,
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InstrItinClass Itin>
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: MMR6Arch<opstr> {
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dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
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string AsmString = !strconcat(opstr, "\t$rt, $offset");
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list<dag> Pattern = [];
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bit isTerminator = 1;
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bit hasDelaySlot = 0;
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InstrItinClass Itinerary = Itin;
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}
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class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
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GPR32Opnd> {
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GPR32Opnd, II_JIALC> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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}
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class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
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GPR32Opnd> {
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GPR32Opnd, II_JIC> {
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bit isBarrier = 1;
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list<Register> Defs = [AT];
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}
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@ -535,65 +552,76 @@ class JRCADDIUSP_MMR6_DESC
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}
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class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> : MMR6Arch<instr_asm> {
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Operand ImmOpnd, InstrItinClass Itin>
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: MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = Itin;
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}
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class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
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class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
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II_ALIGN>;
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class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm> {
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class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass Itin> : MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = Itin;
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}
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class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
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class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
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class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
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class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
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class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm> {
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class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass Itin> : MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = Itin;
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}
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class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
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class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
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class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
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class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
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class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> : MMR6Arch<instr_asm> {
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Operand ImmOpnd, InstrItinClass Itin>
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: MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = Itin;
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}
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class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>;
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class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
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class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> : MMR6Arch<instr_asm> {
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Operand ImmOpnd, InstrItinClass Itin>
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: MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins ImmOpnd:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = Itin;
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}
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class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
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class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
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class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
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simm19_lsl2, II_ADDIUPC>;
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class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
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II_LWPC>;
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class LWP_MMR6_DESC : MMR6Arch<"lwp"> {
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dag OutOperandList = (outs regpair:$rd);
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dag InOperandList = (ins mem_simm12:$addr);
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string AsmString = !strconcat("lwp", "\t$rd, $addr");
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list<dag> Pattern = [];
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InstrItinClass Itin = NoItinerary;
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InstrItinClass Itinerary = II_LWP;
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ComplexPattern Addr = addr;
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Format f = FrmI;
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string BaseOpcode = "lwp";
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@ -606,7 +634,7 @@ class SWP_MMR6_DESC : MMR6Arch<"swp"> {
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dag InOperandList = (ins regpair:$rd, mem_simm12:$addr);
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string AsmString = !strconcat("swp", "\t$rd, $addr");
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list<dag> Pattern = [];
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InstrItinClass Itin = NoItinerary;
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InstrItinClass Itinerary = II_SWP;
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ComplexPattern Addr = addr;
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Format f = FrmI;
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string BaseOpcode = "swp";
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@ -614,17 +642,20 @@ class SWP_MMR6_DESC : MMR6Arch<"swp"> {
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bit mayStore = 1;
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}
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|
||||
class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
|
||||
: MMR6Arch<instr_asm> {
|
||||
class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
||||
InstrItinClass Itin> : MMR6Arch<instr_asm> {
|
||||
dag OutOperandList = (outs GPROpnd:$rd);
|
||||
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
|
||||
class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
|
||||
class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
|
||||
class PAUSE_MMR6_DESC : Barrier<"pause">;
|
||||
class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
|
||||
II_SELCCZ>;
|
||||
class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
|
||||
II_SELCCZ>;
|
||||
class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
|
||||
class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
|
||||
dag OutOperandList = (outs GPR32Opnd:$rt);
|
||||
dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
|
||||
@ -635,10 +666,14 @@ class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
|
||||
}
|
||||
|
||||
class WAIT_MMR6_DESC : WaitMM<"wait">;
|
||||
class SSNOP_MMR6_DESC : Barrier<"ssnop">;
|
||||
// FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
|
||||
// Assemblers targeting specifically Release 6 should reject the SSNOP
|
||||
// instruction with an error.
|
||||
class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
|
||||
class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
|
||||
|
||||
class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
|
||||
InstrItinClass Itin,
|
||||
SDPatternOperator OpNode=null_frag>
|
||||
: MipsR6Inst {
|
||||
dag OutOperandList = (outs GPROpnd:$rd);
|
||||
@ -649,15 +684,16 @@ class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
|
||||
Format f = FrmR;
|
||||
let isCommutable = 0;
|
||||
let isReMaterializable = 1;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
|
||||
// This instruction doesn't trap division by zero itself. We must insert
|
||||
// teq instructions as well.
|
||||
bit usesCustomInserter = 1;
|
||||
}
|
||||
class DIV_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, sdiv>;
|
||||
class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, udiv>;
|
||||
class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, srem>;
|
||||
class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, urem>;
|
||||
class DIV_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
|
||||
class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
|
||||
class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
|
||||
class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
|
||||
class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
|
||||
class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
|
||||
class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
|
||||
@ -671,19 +707,21 @@ class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
|
||||
immZExt16, xor>;
|
||||
|
||||
class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
|
||||
SDPatternOperator OpNode = null_frag,
|
||||
InstrItinClass Itin = NoItinerary,
|
||||
SDPatternOperator OpNode = null_frag,
|
||||
ComplexPattern Addr = addr> :
|
||||
InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
|
||||
let DecoderMethod = "DecodeMem";
|
||||
let mayStore = 1;
|
||||
}
|
||||
class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
|
||||
class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
|
||||
class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
|
||||
InstrItinClass Itinerary = II_SW;
|
||||
}
|
||||
class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9, II_SWE>;
|
||||
|
||||
class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
|
||||
: MMR6Arch<instr_asm> {
|
||||
class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
|
||||
InstrItinClass Itin> : MMR6Arch<instr_asm> {
|
||||
dag InOperandList = (ins RO:$rs);
|
||||
dag OutOperandList = (outs RO:$rt);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
|
||||
@ -691,18 +729,21 @@ class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
|
||||
Format f = FrmR;
|
||||
string BaseOpcode = instr_asm;
|
||||
bit hasSideEffects = 0;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
|
||||
class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
|
||||
class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
|
||||
II_WRPGPR>;
|
||||
class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
|
||||
|
||||
class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
|
||||
RegisterOperand SrcRC> {
|
||||
RegisterOperand SrcRC, InstrItinClass Itin> {
|
||||
dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
|
||||
dag OutOperandList = (outs DstRC:$rs);
|
||||
string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
|
||||
list<dag> Pattern = [];
|
||||
Format f = FrmFR;
|
||||
string BaseOpcode = opstr;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class MTC1_MMR6_DESC_BASE<
|
||||
string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
||||
@ -731,34 +772,42 @@ class MTC1_64_MMR6_DESC_BASE<
|
||||
let Constraints = "$fs = $fs_in";
|
||||
}
|
||||
class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
|
||||
RegisterOperand SrcRC> {
|
||||
RegisterOperand SrcRC, InstrItinClass Itin> {
|
||||
dag InOperandList = (ins SrcRC:$rt);
|
||||
dag OutOperandList = (outs DstRC:$impl);
|
||||
string AsmString = !strconcat(opstr, "\t$rt, $impl");
|
||||
list<dag> Pattern = [];
|
||||
Format f = FrmFR;
|
||||
string BaseOpcode = opstr;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
|
||||
class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd>;
|
||||
class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
|
||||
II_MTC0>;
|
||||
class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
|
||||
II_MTC1, bitconvert>, HARDFLOAT;
|
||||
class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd>;
|
||||
class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd>;
|
||||
class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, GPR32Opnd>,
|
||||
class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
|
||||
II_MTC2>;
|
||||
class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
|
||||
II_MTC0>;
|
||||
class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd,
|
||||
GPR32Opnd, II_MTC1>,
|
||||
HARDFLOAT, FGR_32;
|
||||
class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd, GPR32Opnd>,
|
||||
class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd,
|
||||
GPR32Opnd, II_MTC1>,
|
||||
HARDFLOAT, FGR_64;
|
||||
class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>;
|
||||
class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
|
||||
II_MTC2>;
|
||||
|
||||
class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
|
||||
RegisterOperand SrcRC> {
|
||||
RegisterOperand SrcRC, InstrItinClass Itin> {
|
||||
dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
|
||||
dag OutOperandList = (outs DstRC:$rt);
|
||||
string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
|
||||
list<dag> Pattern = [];
|
||||
Format f = FrmFR;
|
||||
string BaseOpcode = opstr;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
|
||||
RegisterOperand SrcRC,
|
||||
@ -773,24 +822,29 @@ class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
|
||||
string BaseOpcode = opstr;
|
||||
}
|
||||
class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
|
||||
RegisterOperand SrcRC> {
|
||||
RegisterOperand SrcRC, InstrItinClass Itin> {
|
||||
dag InOperandList = (ins SrcRC:$impl);
|
||||
dag OutOperandList = (outs DstRC:$rt);
|
||||
string AsmString = !strconcat(opstr, "\t$rt, $impl");
|
||||
list<dag> Pattern = [];
|
||||
Format f = FrmFR;
|
||||
string BaseOpcode = opstr;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd>;
|
||||
class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
|
||||
II_MFC0>;
|
||||
class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
|
||||
II_MFC1, bitconvert>, HARDFLOAT;
|
||||
class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd>;
|
||||
class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd>;
|
||||
class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
|
||||
II_MFC2>;
|
||||
class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
|
||||
II_MFC0>;
|
||||
class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
|
||||
II_MFHC1>, HARDFLOAT, FGR_32;
|
||||
class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd,
|
||||
II_MFHC1>, HARDFLOAT, FGR_64;
|
||||
class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>;
|
||||
class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
|
||||
II_MFC2>;
|
||||
|
||||
class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
|
||||
dag InOperandList = (ins mem_mm_16:$addr);
|
||||
@ -816,33 +870,33 @@ class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
|
||||
let DecoderMethod = "DecodeFMemMMR2";
|
||||
}
|
||||
|
||||
class LDC2_LWC2_MMR6_DESC_BASE<string opstr> {
|
||||
class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
|
||||
dag OutOperandList = (outs COP2Opnd:$rt);
|
||||
dag InOperandList = (ins mem_mm_11:$addr);
|
||||
string AsmString = !strconcat(opstr, "\t$rt, $addr");
|
||||
list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
|
||||
Format f = FrmFI;
|
||||
InstrItinClass Itinerary = NoItinerary;
|
||||
InstrItinClass Itinerary = itin;
|
||||
string BaseOpcode = opstr;
|
||||
bit mayLoad = 1;
|
||||
string DecoderMethod = "DecodeFMemCop2MMR6";
|
||||
}
|
||||
class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2">;
|
||||
class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2">;
|
||||
class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
|
||||
class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
|
||||
|
||||
class SDC2_SWC2_MMR6_DESC_BASE<string opstr> {
|
||||
class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
|
||||
string AsmString = !strconcat(opstr, "\t$rt, $addr");
|
||||
list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
|
||||
Format f = FrmFI;
|
||||
InstrItinClass Itinerary = NoItinerary;
|
||||
InstrItinClass Itinerary = itin;
|
||||
string BaseOpcode = opstr;
|
||||
bit mayStore = 1;
|
||||
string DecoderMethod = "DecodeFMemCop2MMR6";
|
||||
}
|
||||
class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2">;
|
||||
class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2">;
|
||||
class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
|
||||
class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
|
||||
|
||||
/// Floating Point Instructions
|
||||
class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
|
||||
@ -871,10 +925,14 @@ class FDIV_S_MMR6_DESC
|
||||
: FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
|
||||
class FDIV_D_MMR6_DESC
|
||||
: FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
|
||||
class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
|
||||
class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
|
||||
class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
|
||||
class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
|
||||
class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
|
||||
II_MADDF_S>, HARDFLOAT;
|
||||
class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
|
||||
II_MADDF_D>, HARDFLOAT;
|
||||
class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
|
||||
II_MSUBF_S>, HARDFLOAT;
|
||||
class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
|
||||
II_MSUBF_D>, HARDFLOAT;
|
||||
|
||||
class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
|
||||
RegisterOperand SrcRC, InstrItinClass Itin,
|
||||
@ -896,15 +954,23 @@ class FNEG_S_MMR6_DESC
|
||||
class FNEG_D_MMR6_DESC
|
||||
: FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
|
||||
|
||||
class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
|
||||
class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
|
||||
class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
|
||||
class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
|
||||
class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
|
||||
HARDFLOAT;
|
||||
class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
|
||||
HARDFLOAT;
|
||||
class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
|
||||
HARDFLOAT;
|
||||
class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
|
||||
HARDFLOAT;
|
||||
|
||||
class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
|
||||
class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
|
||||
class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
|
||||
class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
|
||||
class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
|
||||
HARDFLOAT;
|
||||
class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
|
||||
HARDFLOAT;
|
||||
class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
|
||||
HARDFLOAT;
|
||||
class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
|
||||
HARDFLOAT;
|
||||
|
||||
class CVT_MMR6_DESC_BASE<
|
||||
string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
|
||||
@ -940,70 +1006,70 @@ class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
|
||||
II_CVT>, FGR_64;
|
||||
|
||||
multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
|
||||
RegisterOperand FGROpnd> {
|
||||
RegisterOperand FGROpnd, InstrItinClass Itin> {
|
||||
def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
|
||||
CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
|
||||
CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
|
||||
CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
|
||||
CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
|
||||
CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
|
||||
CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
|
||||
CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
|
||||
CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
|
||||
CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
|
||||
CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
|
||||
CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
|
||||
CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
|
||||
CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
|
||||
CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
|
||||
CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
|
||||
!strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
|
||||
CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT,
|
||||
CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
|
||||
ISA_MICROMIPS32R6;
|
||||
}
|
||||
|
||||
@ -1069,49 +1135,63 @@ class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
|
||||
class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
|
||||
FGR64Opnd, II_ROUND>;
|
||||
|
||||
class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
|
||||
class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
|
||||
class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
|
||||
class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D> {
|
||||
// We must insert a SUBREG_TO_REG around $fd_in
|
||||
bit usesCustomInserter = 1;
|
||||
}
|
||||
|
||||
class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
|
||||
class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
|
||||
class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
|
||||
class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
|
||||
class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
|
||||
class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
|
||||
class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
|
||||
class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
|
||||
class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
|
||||
II_SELCCZ_S>;
|
||||
class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
|
||||
II_SELCCZ_D>;
|
||||
class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
|
||||
II_SELCCZ_S>;
|
||||
class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
|
||||
II_SELCCZ_D>;
|
||||
class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
|
||||
II_RINT_S>;
|
||||
class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
|
||||
II_RINT_S>;
|
||||
class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
|
||||
II_CLASS_S>;
|
||||
class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
|
||||
II_CLASS_S>;
|
||||
|
||||
class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
|
||||
class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
|
||||
InstrItinClass Itin>
|
||||
: Store<opstr, RO>, MMR6Arch<opstr> {
|
||||
let DecoderMethod = "DecodeMemMMImm16";
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
|
||||
class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
|
||||
|
||||
class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
|
||||
class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
|
||||
InstrItinClass Itin>
|
||||
: MMR6Arch<instr_asm>, MipsR6Inst {
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins RO:$rt, mem_simm9:$addr);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
|
||||
string DecoderMethod = "DecodeStoreEvaOpMM";
|
||||
bit mayStore = 1;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
|
||||
class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
|
||||
class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
|
||||
class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
|
||||
class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
|
||||
MMR6Arch<instr_asm>, MipsR6Inst {
|
||||
class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd, II_SBE>;
|
||||
class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd, II_SCE>;
|
||||
class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
|
||||
class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd, II_SHE>;
|
||||
class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
|
||||
InstrItinClass Itin>
|
||||
: MMR6Arch<instr_asm>, MipsR6Inst {
|
||||
dag OutOperandList = (outs RO:$rt);
|
||||
dag InOperandList = (ins mem_simm9:$addr);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
|
||||
string DecoderMethod = "DecodeMemMMImm9";
|
||||
bit mayLoad = 1;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
|
||||
class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
|
||||
class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd, II_LLE>;
|
||||
class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd, II_LWE>;
|
||||
class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
|
||||
MMR6Arch<"addu16"> {
|
||||
int AddedComplexity = 1;
|
||||
@ -1133,13 +1213,13 @@ class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
|
||||
MMR6Arch<"sll16">;
|
||||
class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
|
||||
MMR6Arch<"srl16">;
|
||||
class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"break16">,
|
||||
class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">,
|
||||
MicroMipsR6Inst16;
|
||||
class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
|
||||
MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
|
||||
class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
|
||||
MicroMipsR6Inst16;
|
||||
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
|
||||
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">,
|
||||
MicroMipsR6Inst16;
|
||||
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
|
||||
MMR6Arch<"subu16">, MicroMipsR6Inst16 {
|
||||
@ -1177,7 +1257,7 @@ class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
|
||||
dag InOperandList = (ins uimm5:$stype);
|
||||
string AsmString = !strconcat("sync", "\t$stype");
|
||||
list<dag> Pattern = [(MipsSync immZExt5:$stype)];
|
||||
InstrItinClass Itinerary = NoItinerary;
|
||||
InstrItinClass Itinerary = II_SYNC;
|
||||
bit HasSideEffects = 1;
|
||||
}
|
||||
|
||||
@ -1189,6 +1269,7 @@ class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
|
||||
dag OutOperandList = (outs GPR32Opnd:$rt);
|
||||
dag InOperandList = (ins GPR32Opnd:$rd);
|
||||
string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
|
||||
InstrItinClass Itinerary = II_RDPGPR;
|
||||
}
|
||||
|
||||
class SDBBP_MMR6_DESC : MipsR6Inst {
|
||||
@ -1196,27 +1277,26 @@ class SDBBP_MMR6_DESC : MipsR6Inst {
|
||||
dag InOperandList = (ins uimm20:$code_);
|
||||
string AsmString = !strconcat("sdbbp", "\t$code_");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = II_SDBBP;
|
||||
}
|
||||
|
||||
class LWM16_MMR6_DESC
|
||||
: MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
|
||||
!strconcat("lwm16", "\t$rt, $addr"), [],
|
||||
NoItinerary, FrmI>,
|
||||
II_LWM, FrmI>,
|
||||
MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
|
||||
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
|
||||
let mayLoad = 1;
|
||||
InstrItinClass Itin = NoItinerary;
|
||||
ComplexPattern Addr = addr;
|
||||
}
|
||||
|
||||
class SWM16_MMR6_DESC
|
||||
: MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
|
||||
!strconcat("swm16", "\t$rt, $addr"), [],
|
||||
NoItinerary, FrmI>,
|
||||
II_SWM, FrmI>,
|
||||
MMR6Arch<"swm16">, MicroMipsR6Inst16 {
|
||||
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
|
||||
let mayStore = 1;
|
||||
InstrItinClass Itin = NoItinerary;
|
||||
ComplexPattern Addr = addr;
|
||||
}
|
||||
|
||||
@ -1249,31 +1329,33 @@ class JALRC_HB_MMR6_DESC {
|
||||
dag InOperandList = (ins GPR32Opnd:$rs);
|
||||
string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = NoItinerary;
|
||||
InstrItinClass Itinerary = II_JALR_HB;
|
||||
Format Form = FrmJ;
|
||||
bit isIndirectBranch = 1;
|
||||
bit hasDelaySlot = 0;
|
||||
}
|
||||
|
||||
class TLBINV_MMR6_DESC_BASE<string opstr> {
|
||||
class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins);
|
||||
string AsmString = opstr;
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
|
||||
class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">;
|
||||
class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">;
|
||||
class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
|
||||
class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
|
||||
|
||||
class DVPEVP_MMR6_DESC_BASE<string opstr> {
|
||||
class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins GPR32Opnd:$rs);
|
||||
string AsmString = !strconcat(opstr, "\t$rs");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
|
||||
class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">;
|
||||
class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">;
|
||||
class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
|
||||
class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
|
||||
|
||||
class BEQZC_MMR6_DESC
|
||||
: CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
|
||||
@ -1292,15 +1374,17 @@ class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
|
||||
class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
|
||||
class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
|
||||
|
||||
class BRANCH_COP2_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE {
|
||||
class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
|
||||
: BRANCH_DESC_BASE {
|
||||
dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
|
||||
dag OutOperandList = (outs);
|
||||
string AsmString = !strconcat(opstr, "\t$rt, $offset");
|
||||
list<Register> Defs = [AT];
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
|
||||
class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">;
|
||||
class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">;
|
||||
class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
|
||||
class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
|
||||
|
||||
class EXT_MMR6_DESC {
|
||||
dag OutOperandList = (outs GPR32Opnd:$rt);
|
||||
@ -1344,6 +1428,7 @@ class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
|
||||
dag OutOperandList = (outs);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
|
||||
list<Register> Defs = [AT];
|
||||
InstrItinClass Itinerary = II_BCCC;
|
||||
}
|
||||
|
||||
class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
|
||||
@ -1547,8 +1632,8 @@ def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
|
||||
ISA_MICROMIPS32R6;
|
||||
def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
|
||||
ISA_MICROMIPS32R6;
|
||||
defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
|
||||
defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
|
||||
defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
|
||||
defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
|
||||
def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
|
||||
def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
|
||||
def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
|
||||
|
||||
@ -74,24 +74,28 @@ class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
|
||||
class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
||||
InstrItinClass Itin>
|
||||
: MMR6Arch<instr_asm>, MipsR6Inst {
|
||||
dag OutOperandList = (outs GPROpnd:$rt);
|
||||
dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
|
||||
class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
|
||||
|
||||
class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
|
||||
class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
||||
InstrItinClass Itin>
|
||||
: MMR6Arch<instr_asm>, MipsR6Inst {
|
||||
dag OutOperandList = (outs GPROpnd:$rs);
|
||||
dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
|
||||
string Constraints = "$rs = $rt";
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
|
||||
class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
|
||||
class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
|
||||
class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
|
||||
|
||||
class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
|
||||
Operand SizeOpnd, SDPatternOperator Op = null_frag>
|
||||
@ -115,26 +119,33 @@ class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
|
||||
uimm5_plus1, MipsExt>;
|
||||
|
||||
class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
||||
Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
|
||||
Operand ImmOpnd, InstrItinClass itin>
|
||||
: MMR6Arch<instr_asm>, MipsR6Inst {
|
||||
dag OutOperandList = (outs GPROpnd:$rd);
|
||||
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
|
||||
class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
|
||||
class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3,
|
||||
II_DALIGN>;
|
||||
|
||||
class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
|
||||
class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, srem>;
|
||||
class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
|
||||
class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, urem>;
|
||||
class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV,
|
||||
sdiv>;
|
||||
class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, II_DMOD,
|
||||
srem>;
|
||||
class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU,
|
||||
udiv>;
|
||||
class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU,
|
||||
urem>;
|
||||
|
||||
class DCLO_MM64R6_DESC {
|
||||
dag OutOperandList = (outs GPR64Opnd:$rt);
|
||||
dag InOperandList = (ins GPR64Opnd:$rs);
|
||||
string AsmString = !strconcat("dclo", "\t$rt, $rs");
|
||||
list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz (not GPR64Opnd:$rs)))];
|
||||
InstrItinClass Itinerary = II_CLO;
|
||||
InstrItinClass Itinerary = II_DCLO;
|
||||
Format Form = FrmR;
|
||||
string BaseOpcode = "dclo";
|
||||
}
|
||||
@ -144,7 +155,7 @@ class DCLZ_MM64R6_DESC {
|
||||
dag InOperandList = (ins GPR64Opnd:$rs);
|
||||
string AsmString = !strconcat("dclz", "\t$rt, $rs");
|
||||
list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz GPR64Opnd:$rs))];
|
||||
InstrItinClass Itinerary = II_CLZ;
|
||||
InstrItinClass Itinerary = II_DCLZ;
|
||||
Format Form = FrmR;
|
||||
string BaseOpcode = "dclz";
|
||||
}
|
||||
@ -154,16 +165,18 @@ class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
|
||||
class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
|
||||
class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
|
||||
MipsIns>;
|
||||
class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd>;
|
||||
class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd,
|
||||
II_DMTC0>;
|
||||
class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
|
||||
II_DMTC1, bitconvert>;
|
||||
class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>;
|
||||
|
||||
class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>;
|
||||
class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd,
|
||||
II_DMTC2>;
|
||||
class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd,
|
||||
II_DMFC0>;
|
||||
class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
|
||||
II_DMFC1, bitconvert>;
|
||||
class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>;
|
||||
|
||||
class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd,
|
||||
II_DMFC2>;
|
||||
class DADD_MM64R6_DESC : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>;
|
||||
class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
|
||||
II_DADDIU, immSExt16, add>,
|
||||
@ -188,7 +201,8 @@ class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
|
||||
class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
|
||||
class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
|
||||
|
||||
class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
|
||||
class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3,
|
||||
II_LDPC>;
|
||||
|
||||
class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
|
||||
InstrItinClass Itin = NoItinerary,
|
||||
@ -207,19 +221,20 @@ class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
|
||||
class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
|
||||
mulhu>;
|
||||
|
||||
class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
|
||||
class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
||||
InstrItinClass Itin> {
|
||||
dag OutOperandList = (outs GPROpnd:$rt);
|
||||
dag InOperandList = (ins GPROpnd:$rs);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
|
||||
bit hasSideEffects = 0;
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = NoItinerary;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
Format Form = FrmR;
|
||||
string BaseOpcode = instr_asm;
|
||||
}
|
||||
|
||||
class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd>;
|
||||
class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd>;
|
||||
class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd, II_DSBH>;
|
||||
class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd, II_DSHD>;
|
||||
|
||||
class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd,
|
||||
InstrItinClass itin,
|
||||
|
||||
@ -194,20 +194,20 @@ class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
|
||||
|
||||
let canFoldAsLoad = 1 in
|
||||
class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
|
||||
Operand MemOpnd> :
|
||||
Operand MemOpnd, InstrItinClass Itin> :
|
||||
InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
|
||||
!strconcat(opstr, "\t$rt, $addr"),
|
||||
[(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
|
||||
NoItinerary, FrmI> {
|
||||
Itin, FrmI> {
|
||||
let DecoderMethod = "DecodeMemMMImm12";
|
||||
string Constraints = "$src = $rt";
|
||||
}
|
||||
|
||||
class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
|
||||
Operand MemOpnd>:
|
||||
Operand MemOpnd, InstrItinClass Itin>:
|
||||
InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"),
|
||||
[(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
|
||||
[(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
|
||||
let DecoderMethod = "DecodeMemMMImm12";
|
||||
}
|
||||
|
||||
@ -248,39 +248,37 @@ def regpair : Operand<i32> {
|
||||
let MIOperandInfo = (ops ptr_rc, ptr_rc);
|
||||
}
|
||||
|
||||
class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
|
||||
ComplexPattern Addr = addr> :
|
||||
InstSE<(outs), (ins regpair:$rt, mem_simm12:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
|
||||
class StorePairMM<string opstr, ComplexPattern Addr = addr>
|
||||
: InstSE<(outs), (ins regpair:$rt, mem_simm12:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {
|
||||
let DecoderMethod = "DecodeMemMMImm12";
|
||||
let mayStore = 1;
|
||||
}
|
||||
|
||||
class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
|
||||
ComplexPattern Addr = addr> :
|
||||
InstSE<(outs regpair:$rt), (ins mem_simm12:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
|
||||
class LoadPairMM<string opstr, ComplexPattern Addr = addr>
|
||||
: InstSE<(outs regpair:$rt), (ins mem_simm12:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {
|
||||
let DecoderMethod = "DecodeMemMMImm12";
|
||||
let mayLoad = 1;
|
||||
}
|
||||
|
||||
class LLBaseMM<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> {
|
||||
let DecoderMethod = "DecodeMemMMImm12";
|
||||
let mayLoad = 1;
|
||||
}
|
||||
|
||||
class LLEBaseMM<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {
|
||||
let DecoderMethod = "DecodeMemMMImm9";
|
||||
let mayLoad = 1;
|
||||
}
|
||||
|
||||
class SCBaseMM<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
|
||||
let DecoderMethod = "DecodeMemMMImm12";
|
||||
let mayStore = 1;
|
||||
let Constraints = "$rt = $dst";
|
||||
@ -288,7 +286,7 @@ class SCBaseMM<string opstr, RegisterOperand RO> :
|
||||
|
||||
class SCEBaseMM<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
|
||||
let DecoderMethod = "DecodeMemMMImm9";
|
||||
let mayStore = 1;
|
||||
let Constraints = "$rt = $dst";
|
||||
@ -331,7 +329,7 @@ class LogicRMM16<string opstr, RegisterOperand RO,
|
||||
class NotMM16<string opstr, RegisterOperand RO> :
|
||||
MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
|
||||
!strconcat(opstr, "\t$rt, $rs"),
|
||||
[(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
|
||||
[(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
|
||||
|
||||
class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
|
||||
InstrItinClass Itin = NoItinerary> :
|
||||
@ -385,23 +383,23 @@ class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
|
||||
class AddImmUR2<string opstr, RegisterOperand RO> :
|
||||
MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
|
||||
!strconcat(opstr, "\t$rd, $rs, $imm"),
|
||||
[], NoItinerary, FrmR> {
|
||||
[], II_ADDIU, FrmR> {
|
||||
let isCommutable = 1;
|
||||
}
|
||||
|
||||
class AddImmUS5<string opstr, RegisterOperand RO> :
|
||||
MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
|
||||
!strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
|
||||
!strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR> {
|
||||
let Constraints = "$rd = $dst";
|
||||
}
|
||||
|
||||
class AddImmUR1SP<string opstr, RegisterOperand RO> :
|
||||
MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
|
||||
!strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
|
||||
!strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR>;
|
||||
|
||||
class AddImmUSP<string opstr> :
|
||||
MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
|
||||
!strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
|
||||
!strconcat(opstr, "\t$imm"), [], II_ADDIU, FrmI>;
|
||||
|
||||
class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
|
||||
MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
|
||||
@ -410,17 +408,15 @@ class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
|
||||
InstrItinClass Itin = NoItinerary> :
|
||||
MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
|
||||
!strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
|
||||
let isCommutable = isComm;
|
||||
class MoveMM16<string opstr, RegisterOperand RO>
|
||||
: MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
|
||||
!strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> {
|
||||
let isReMaterializable = 1;
|
||||
}
|
||||
|
||||
class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
|
||||
MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
|
||||
!strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
|
||||
!strconcat(opstr, "\t$rd, $imm"), [], II_LI, FrmI> {
|
||||
let isReMaterializable = 1;
|
||||
}
|
||||
|
||||
@ -472,10 +468,10 @@ class JumpRegCMM16<string opstr, RegisterOperand RO> :
|
||||
}
|
||||
|
||||
// Break16 and Sdbbp16
|
||||
class BrkSdbbp16MM<string opstr> :
|
||||
class BrkSdbbp16MM<string opstr, InstrItinClass Itin> :
|
||||
MicroMipsInst16<(outs), (ins uimm4:$code_),
|
||||
!strconcat(opstr, "\t$code_"),
|
||||
[], NoItinerary, FrmOther>;
|
||||
[], Itin, FrmOther>;
|
||||
|
||||
class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
|
||||
MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
|
||||
@ -505,18 +501,17 @@ let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
|
||||
}
|
||||
|
||||
class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
|
||||
InstrItinClass Itin = NoItinerary,
|
||||
SDPatternOperator OpNode = null_frag> :
|
||||
InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
|
||||
!strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
|
||||
!strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;
|
||||
|
||||
class PrefetchIndexed<string opstr> :
|
||||
InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
|
||||
!strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>;
|
||||
!strconcat(opstr, "\t$hint, ${index}(${base})"), [], II_PREF, FrmOther>;
|
||||
|
||||
class AddImmUPC<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
|
||||
!strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
|
||||
!strconcat(opstr, "\t$rs, $imm"), [], II_ADDIU, FrmR>;
|
||||
|
||||
/// A list of registers used by load/store multiple instructions.
|
||||
def RegListAsmOperand : AsmOperandClass {
|
||||
@ -650,16 +645,16 @@ def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
|
||||
def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
|
||||
BEQNEZ_FM_MM16<0x2b>;
|
||||
def B16_MM : UncondBranchMM16<"b16">, B16_FM;
|
||||
def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>,
|
||||
def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
|
||||
ISA_MICROMIPS_NOT_32R6_64R6;
|
||||
def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>,
|
||||
def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
|
||||
ISA_MICROMIPS_NOT_32R6_64R6;
|
||||
|
||||
let DecoderNamespace = "MicroMips" in {
|
||||
/// Load and Store Instructions - multiple
|
||||
def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>,
|
||||
def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
|
||||
ISA_MICROMIPS32_NOT_MIPS32R6;
|
||||
def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>,
|
||||
def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
|
||||
ISA_MICROMIPS32_NOT_MIPS32R6;
|
||||
let AdditionalPredicates = [InMicroMips] in {
|
||||
def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl),
|
||||
@ -673,7 +668,7 @@ let DecoderNamespace = "MicroMips" in {
|
||||
|
||||
class WaitMM<string opstr> :
|
||||
InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
|
||||
NoItinerary, FrmOther, opstr>;
|
||||
II_WAIT, FrmOther, opstr>;
|
||||
|
||||
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips, NotMips32r6,
|
||||
NotMips64r6] in {
|
||||
@ -685,15 +680,15 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips, NotMips32r6,
|
||||
}
|
||||
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
||||
/// Arithmetic Instructions (ALU Immediate)
|
||||
def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
|
||||
def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
|
||||
ADDI_FM_MM<0xc>;
|
||||
def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
|
||||
def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
|
||||
ADDI_FM_MM<0x4>;
|
||||
def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
|
||||
SLTI_FM_MM<0x24>;
|
||||
def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
|
||||
SLTI_FM_MM<0x2c>;
|
||||
def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
|
||||
def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,
|
||||
ADDI_FM_MM<0x34>;
|
||||
def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
|
||||
or>, ADDI_FM_MM<0x14>;
|
||||
@ -709,9 +704,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
||||
ADD_FM_MM<0, 0x150>;
|
||||
def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
|
||||
ADD_FM_MM<0, 0x1d0>;
|
||||
def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
|
||||
def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
|
||||
def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
|
||||
def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL>,
|
||||
ADD_FM_MM<0, 0x210>;
|
||||
def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
|
||||
ADD_FM_MM<0, 0x110>;
|
||||
def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
|
||||
ADD_FM_MM<0, 0x190>;
|
||||
def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
|
||||
def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
|
||||
ADD_FM_MM<0, 0x390>;
|
||||
@ -760,60 +758,69 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
||||
|
||||
/// Load and Store Instructions - aligned
|
||||
let DecoderMethod = "DecodeMemMMImm16" in {
|
||||
def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16>, MMRel, LW_FM_MM<0x7>;
|
||||
def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16>, MMRel, LW_FM_MM<0x5>;
|
||||
def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, null_frag, II_LB>,
|
||||
MMRel, LW_FM_MM<0x7>;
|
||||
def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, null_frag, II_LBU>,
|
||||
MMRel, LW_FM_MM<0x5>;
|
||||
def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
|
||||
addrDefault>, MMRel, LW_FM_MM<0xf>;
|
||||
def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
|
||||
MMRel, LW_FM_MM<0xd>;
|
||||
def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
|
||||
def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
|
||||
def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
|
||||
def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
|
||||
def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>;
|
||||
def SB_MM : Store<"sb", GPR32Opnd, null_frag, II_SB>, MMRel,
|
||||
LW_FM_MM<0x6>;
|
||||
def SH_MM : Store<"sh", GPR32Opnd, null_frag, II_SH>, MMRel,
|
||||
LW_FM_MM<0xe>;
|
||||
def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
|
||||
LW_FM_MM<0x3e>;
|
||||
}
|
||||
|
||||
let DecoderMethod = "DecodeMemMMImm9" in {
|
||||
def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
|
||||
def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
|
||||
def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9>,
|
||||
def LBE_MM : Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
|
||||
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
|
||||
def LBuE_MM : Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
|
||||
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
|
||||
def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag, II_LHE>,
|
||||
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
|
||||
def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9>,
|
||||
def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag, II_LHUE>,
|
||||
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
|
||||
def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9>,
|
||||
def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag, II_LWE>,
|
||||
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
|
||||
def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9>,
|
||||
def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag, II_SBE>,
|
||||
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
|
||||
def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9>,
|
||||
def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag, II_SHE>,
|
||||
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
|
||||
def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9>,
|
||||
def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag, II_SWE>,
|
||||
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
|
||||
}
|
||||
|
||||
def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
|
||||
|
||||
/// Load and Store Instructions - unaligned
|
||||
def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
|
||||
def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12, II_LWL>,
|
||||
LWL_FM_MM<0x0>;
|
||||
def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
|
||||
def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12, II_LWR>,
|
||||
LWL_FM_MM<0x1>;
|
||||
def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
|
||||
def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12, II_SWL>,
|
||||
LWL_FM_MM<0x8>;
|
||||
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
|
||||
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12, II_SWR>,
|
||||
LWL_FM_MM<0x9>;
|
||||
let DecoderMethod = "DecodeMemMMImm9" in {
|
||||
def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9>,
|
||||
POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
|
||||
def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9>,
|
||||
POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
|
||||
def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9>,
|
||||
def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
|
||||
II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
|
||||
def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
|
||||
II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
|
||||
def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
|
||||
II_SWLE>,
|
||||
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
|
||||
def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9>,
|
||||
def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
|
||||
II_SWRE>,
|
||||
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
|
||||
}
|
||||
|
||||
/// Load and Store Instructions - multiple
|
||||
def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
|
||||
def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
|
||||
def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>;
|
||||
def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>;
|
||||
|
||||
/// Load and Store Pair Instructions
|
||||
def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
|
||||
@ -859,9 +866,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
||||
def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
|
||||
|
||||
/// Count Leading
|
||||
def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
|
||||
def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
|
||||
ISA_MIPS32;
|
||||
def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
|
||||
def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
|
||||
ISA_MIPS32;
|
||||
|
||||
/// Sign Ext In Register Instructions.
|
||||
@ -921,29 +928,33 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
||||
/// Control Instructions
|
||||
def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
|
||||
def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
|
||||
def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10>, SYS_FM_MM;
|
||||
def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
|
||||
def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
|
||||
def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
|
||||
def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
|
||||
def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
|
||||
def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>;
|
||||
def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>;
|
||||
def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
|
||||
ISA_MIPS32R2;
|
||||
def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
|
||||
def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
|
||||
ISA_MIPS32R2;
|
||||
|
||||
/// Trap Instructions
|
||||
def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4>, TEQ_FM_MM<0x0>;
|
||||
def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4>, TEQ_FM_MM<0x08>;
|
||||
def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4>, TEQ_FM_MM<0x10>;
|
||||
def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4>, TEQ_FM_MM<0x20>;
|
||||
def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4>, TEQ_FM_MM<0x28>;
|
||||
def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4>, TEQ_FM_MM<0x30>;
|
||||
def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>;
|
||||
def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>;
|
||||
def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,
|
||||
TEQ_FM_MM<0x10>;
|
||||
def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>;
|
||||
def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,
|
||||
TEQ_FM_MM<0x28>;
|
||||
def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>;
|
||||
|
||||
def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
|
||||
def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
|
||||
def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
|
||||
def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
|
||||
def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
|
||||
def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
|
||||
def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>;
|
||||
def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>;
|
||||
def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>,
|
||||
TEQI_FM_MM<0x0b>;
|
||||
def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>;
|
||||
def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,
|
||||
TEQI_FM_MM<0x0a>;
|
||||
def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>;
|
||||
|
||||
/// Load-linked, Store-conditional
|
||||
def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
|
||||
@ -953,28 +964,28 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
||||
def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
|
||||
|
||||
let DecoderMethod = "DecodeCacheOpMM" in {
|
||||
def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
|
||||
def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
|
||||
CACHE_PREF_FM_MM<0x08, 0x6>;
|
||||
def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
|
||||
def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
|
||||
CACHE_PREF_FM_MM<0x18, 0x2>;
|
||||
}
|
||||
|
||||
let DecoderMethod = "DecodePrefeOpMM" in {
|
||||
def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>,
|
||||
def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
|
||||
CACHE_PREFE_FM_MM<0x18, 0x2>;
|
||||
def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>,
|
||||
def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
|
||||
CACHE_PREFE_FM_MM<0x18, 0x3>;
|
||||
}
|
||||
def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
|
||||
def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
|
||||
def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
|
||||
def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>;
|
||||
def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>;
|
||||
def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>;
|
||||
|
||||
def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
|
||||
def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
|
||||
def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
|
||||
def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
|
||||
def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>;
|
||||
def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>;
|
||||
def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>;
|
||||
def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>;
|
||||
|
||||
def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10>, SDBBP_FM_MM;
|
||||
def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM;
|
||||
|
||||
def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
|
||||
}
|
||||
|
||||
@ -80,9 +80,10 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
|
||||
V1 = RegInfo.createVirtualRegister(RC);
|
||||
V2 = RegInfo.createVirtualRegister(RC);
|
||||
|
||||
BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0)
|
||||
.addReg(V1, RegState::Define)
|
||||
.addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI)
|
||||
|
||||
BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
|
||||
.addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
|
||||
BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
|
||||
.addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
|
||||
|
||||
BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
|
||||
|
||||
@ -177,90 +177,98 @@ class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;
|
||||
|
||||
class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
|
||||
RegisterOperand FGROpnd,
|
||||
InstrItinClass Itin,
|
||||
SDPatternOperator Op = null_frag> {
|
||||
dag OutOperandList = (outs FGRCCOpnd:$fd);
|
||||
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
|
||||
string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
|
||||
list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
|
||||
bit isCTI = 1;
|
||||
InstrItinClass Itinerary = Itin;
|
||||
}
|
||||
|
||||
multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
|
||||
RegisterOperand FGROpnd>{
|
||||
RegisterOperand FGROpnd, InstrItinClass Itin>{
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
|
||||
CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.af.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
|
||||
CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
|
||||
CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>,
|
||||
MipsR6Arch<!strconcat("cmp.un.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
|
||||
CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
|
||||
CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin,
|
||||
setoeq>,
|
||||
MipsR6Arch<!strconcat("cmp.eq.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_UEQ>,
|
||||
CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
|
||||
CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin,
|
||||
setueq>,
|
||||
MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
|
||||
CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>,
|
||||
CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin,
|
||||
setolt>,
|
||||
MipsR6Arch<!strconcat("cmp.lt.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_ULT>,
|
||||
CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
|
||||
CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin,
|
||||
setult>,
|
||||
MipsR6Arch<!strconcat("cmp.ult.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
|
||||
CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>,
|
||||
CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin,
|
||||
setole>,
|
||||
MipsR6Arch<!strconcat("cmp.le.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_ULE>,
|
||||
CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
|
||||
CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin,
|
||||
setule>,
|
||||
MipsR6Arch<!strconcat("cmp.ule.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_SAF>,
|
||||
CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.saf.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_SUN>,
|
||||
CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.sun.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_SEQ>,
|
||||
CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.seq.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_SUEQ>,
|
||||
CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_SLT>,
|
||||
CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.slt.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_SULT>,
|
||||
CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.sult.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_SLE>,
|
||||
CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.sle.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
|
||||
FIELD_CMP_COND_SULE>,
|
||||
CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,
|
||||
CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>,
|
||||
MipsR6Arch<!strconcat("cmp.sule.", Typestr)>,
|
||||
ISA_MIPS32R6, HARDFLOAT;
|
||||
}
|
||||
@ -426,6 +434,7 @@ class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
|
||||
string AsmString = instr_asm;
|
||||
bit hasDelaySlot = 1;
|
||||
bit isCTI = 1;
|
||||
InstrItinClass Itinerary = II_BC2CCZ;
|
||||
}
|
||||
|
||||
class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
|
||||
@ -468,6 +477,7 @@ class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
|
||||
bit isTerminator=1;
|
||||
bit isBarrier=1;
|
||||
bit isCTI = 1;
|
||||
InstrItinClass Itinerary = II_JR_HB;
|
||||
}
|
||||
|
||||
class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
||||
@ -540,7 +550,8 @@ class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
|
||||
class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>;
|
||||
class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>;
|
||||
|
||||
class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
||||
class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs FGROpnd:$fd);
|
||||
dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
|
||||
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
|
||||
@ -548,13 +559,16 @@ class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
||||
FGROpnd:$ft,
|
||||
FGROpnd:$fs))];
|
||||
string Constraints = "$fd_in = $fd";
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
|
||||
class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd>, MipsR6Arch<"sel.d"> {
|
||||
class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>,
|
||||
MipsR6Arch<"sel.d"> {
|
||||
// We must insert a SUBREG_TO_REG around $fd_in
|
||||
bit usesCustomInserter = 1;
|
||||
}
|
||||
class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>, MipsR6Arch<"sel.s">;
|
||||
class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>,
|
||||
MipsR6Arch<"sel.s">;
|
||||
|
||||
class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
|
||||
: MipsR6Arch<instr_asm> {
|
||||
@ -583,86 +597,98 @@ class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>;
|
||||
class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>;
|
||||
class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>;
|
||||
|
||||
class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
||||
class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs FGROpnd:$fd);
|
||||
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
|
||||
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
|
||||
class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
|
||||
class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
|
||||
class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
|
||||
class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
|
||||
class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>;
|
||||
class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>;
|
||||
class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>;
|
||||
class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>;
|
||||
|
||||
class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
|
||||
class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
|
||||
class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
|
||||
class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
|
||||
class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAX_S>;
|
||||
class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAX_D>;
|
||||
class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MIN_D>;
|
||||
class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MIN_S>;
|
||||
|
||||
class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
||||
class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs FGROpnd:$fd);
|
||||
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
|
||||
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
|
||||
class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>,
|
||||
class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, II_SELCCZ_S>,
|
||||
MipsR6Arch<"seleqz.s">;
|
||||
class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>,
|
||||
class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, II_SELCCZ_D>,
|
||||
MipsR6Arch<"seleqz.d">;
|
||||
class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>,
|
||||
class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, II_SELCCZ_S>,
|
||||
MipsR6Arch<"selnez.s">;
|
||||
class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>,
|
||||
class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, II_SELCCZ_D>,
|
||||
MipsR6Arch<"selnez.d">;
|
||||
|
||||
class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
||||
class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs FGROpnd:$fd);
|
||||
dag InOperandList = (ins FGROpnd:$fs);
|
||||
string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
|
||||
list<dag> Pattern = [];
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
|
||||
class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
|
||||
class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
|
||||
class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
|
||||
class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
|
||||
class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, II_RINT_S>;
|
||||
class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>;
|
||||
class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>;
|
||||
class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>;
|
||||
|
||||
class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
|
||||
RegisterOperand GPROpnd> : MipsR6Arch<instr_asm> {
|
||||
RegisterOperand GPROpnd, InstrItinClass itin>
|
||||
: MipsR6Arch<instr_asm> {
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
|
||||
string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
|
||||
list<dag> Pattern = [];
|
||||
string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
|
||||
class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
|
||||
class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>;
|
||||
class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd, II_CACHE>;
|
||||
class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd, II_PREF>;
|
||||
|
||||
class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
|
||||
class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs COPOpnd:$rt);
|
||||
dag InOperandList = (ins mem_simm11:$addr);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
|
||||
list<dag> Pattern = [];
|
||||
bit mayLoad = 1;
|
||||
string DecoderMethod = "DecodeFMemCop2R6";
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
|
||||
class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
|
||||
class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>;
|
||||
class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd, II_LDC2>;
|
||||
class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd, II_LWC2>;
|
||||
|
||||
class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
|
||||
class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
|
||||
list<dag> Pattern = [];
|
||||
bit mayStore = 1;
|
||||
string DecoderMethod = "DecodeFMemCop2R6";
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
|
||||
class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;
|
||||
class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>;
|
||||
class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd, II_SDC2>;
|
||||
class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd, II_SWC2>;
|
||||
|
||||
class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
||||
Operand ImmOpnd, InstrItinClass itin>
|
||||
@ -732,6 +758,7 @@ class SDBBP_R6_DESC {
|
||||
string AsmString = "sdbbp\t$code_";
|
||||
list<dag> Pattern = [];
|
||||
bit isCTI = 1;
|
||||
InstrItinClass Itinerary = II_SDBBP;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -786,8 +813,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
}
|
||||
def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
|
||||
def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
|
||||
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
|
||||
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
|
||||
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>;
|
||||
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
|
||||
def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
|
||||
|
||||
@ -295,14 +295,16 @@ def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
|
||||
|
||||
/// Count Leading
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>,
|
||||
ISA_MIPS64_NOT_64R6;
|
||||
def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>,
|
||||
ISA_MIPS64_NOT_64R6;
|
||||
def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd, II_DCLZ>,
|
||||
CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
|
||||
def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd, II_DCLO>,
|
||||
CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
|
||||
|
||||
/// Double Word Swap Bytes/HalfWords
|
||||
def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
|
||||
def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
|
||||
def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>,
|
||||
ISA_MIPS64R2;
|
||||
def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>,
|
||||
ISA_MIPS64R2;
|
||||
}
|
||||
|
||||
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
|
||||
@ -359,11 +361,12 @@ class Count1s<string opstr, RegisterOperand RO>:
|
||||
let TwoOperandAliasConstraint = "$rd = $rs";
|
||||
}
|
||||
|
||||
class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
|
||||
class ExtsCins<string opstr, InstrItinClass itin,
|
||||
SDPatternOperator Op = null_frag>:
|
||||
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
|
||||
!strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
|
||||
[(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
|
||||
NoItinerary, FrmR, opstr> {
|
||||
itin, FrmR, opstr> {
|
||||
let TwoOperandAliasConstraint = "$rt = $rs";
|
||||
}
|
||||
|
||||
@ -397,9 +400,9 @@ class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
|
||||
let Defs = [AT];
|
||||
}
|
||||
|
||||
class MFC2OP<string asmstr, RegisterOperand RO> :
|
||||
class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> :
|
||||
InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
|
||||
!strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>;
|
||||
!strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>;
|
||||
|
||||
// Unsigned Byte Add
|
||||
def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
|
||||
@ -427,12 +430,12 @@ def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
|
||||
}
|
||||
|
||||
// Extract a signed bit field /+32
|
||||
def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>, ASE_CNMIPS;
|
||||
def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>, ASE_CNMIPS;
|
||||
def EXTS : ExtsCins<"exts", II_EXT>, EXTS_FM<0x3a>, ASE_CNMIPS;
|
||||
def EXTS32: ExtsCins<"exts32", II_EXT>, EXTS_FM<0x3b>, ASE_CNMIPS;
|
||||
|
||||
// Clear and insert a bit field /+32
|
||||
def CINS : ExtsCins<"cins">, EXTS_FM<0x32>, ASE_CNMIPS;
|
||||
def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>, ASE_CNMIPS;
|
||||
def CINS : ExtsCins<"cins", II_INS>, EXTS_FM<0x32>, ASE_CNMIPS;
|
||||
def CINS32: ExtsCins<"cins32", II_INS>, EXTS_FM<0x33>, ASE_CNMIPS;
|
||||
|
||||
// Move to multiplier/product register
|
||||
def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>,
|
||||
@ -474,8 +477,10 @@ def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>,
|
||||
}
|
||||
|
||||
// Move between CPU and coprocessor registers
|
||||
def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>, ASE_CNMIPS;
|
||||
def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>, ASE_CNMIPS;
|
||||
def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd, II_DMFC2>, MFC2OP_FM<0x12, 1>,
|
||||
ASE_CNMIPS;
|
||||
def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>,
|
||||
ASE_CNMIPS;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@ -90,12 +90,13 @@ class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>;
|
||||
class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;
|
||||
|
||||
class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
|
||||
GPR64Opnd> {
|
||||
GPR64Opnd, II_JIALC> {
|
||||
bit isCall = 1;
|
||||
list<Register> Defs = [RA];
|
||||
}
|
||||
|
||||
class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
|
||||
class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd,
|
||||
II_JIC> {
|
||||
bit isBarrier = 1;
|
||||
bit isTerminator = 1;
|
||||
list<Register> Defs = [AT];
|
||||
|
||||
@ -44,6 +44,7 @@ def II_BC1FL : InstrItinClass;
|
||||
def II_BC1T : InstrItinClass;
|
||||
def II_BC1TL : InstrItinClass;
|
||||
def II_BC1CCZ : InstrItinClass;
|
||||
def II_BC2CCZ : InstrItinClass;
|
||||
def II_BCC : InstrItinClass; // beq and bne
|
||||
def II_BCCZ : InstrItinClass; // b[gl][et]z
|
||||
def II_BCCC : InstrItinClass; // b<cc>c
|
||||
@ -61,6 +62,10 @@ def II_CTC2 : InstrItinClass;
|
||||
def II_CVT : InstrItinClass;
|
||||
def II_C_CC_D : InstrItinClass; // Any c.<cc>.d instruction
|
||||
def II_C_CC_S : InstrItinClass; // Any c.<cc>.s instruction
|
||||
def II_CMP_CC_D : InstrItinClass; // Any cmp.<cc>.d instruction
|
||||
def II_CMP_CC_S : InstrItinClass; // Any cmp.<cc>.s instruction
|
||||
def II_CLASS_D : InstrItinClass;
|
||||
def II_CLASS_S : InstrItinClass;
|
||||
def II_DADDIU : InstrItinClass;
|
||||
def II_DADDU : InstrItinClass;
|
||||
def II_DADDI : InstrItinClass;
|
||||
@ -174,6 +179,7 @@ def II_LHE : InstrItinClass;
|
||||
def II_LHU : InstrItinClass;
|
||||
def II_LHUE : InstrItinClass;
|
||||
def II_LL : InstrItinClass;
|
||||
def II_LI : InstrItinClass;
|
||||
def II_LLD : InstrItinClass;
|
||||
def II_LUI : InstrItinClass;
|
||||
def II_LUXC1 : InstrItinClass;
|
||||
@ -182,14 +188,17 @@ def II_LWE : InstrItinClass;
|
||||
def II_LWC1 : InstrItinClass;
|
||||
def II_LWC2 : InstrItinClass;
|
||||
def II_LWC3 : InstrItinClass;
|
||||
def II_LWM : InstrItinClass;
|
||||
def II_LWL : InstrItinClass;
|
||||
def II_LWLE : InstrItinClass;
|
||||
def II_LWPC : InstrItinClass;
|
||||
def II_LWP : InstrItinClass;
|
||||
def II_LWR : InstrItinClass;
|
||||
def II_LWRE : InstrItinClass;
|
||||
def II_LWU : InstrItinClass;
|
||||
def II_LWUPC : InstrItinClass;
|
||||
def II_LWXC1 : InstrItinClass;
|
||||
def II_LWXS : InstrItinClass;
|
||||
def II_LSA : InstrItinClass;
|
||||
def II_DLSA : InstrItinClass;
|
||||
def II_MADD : InstrItinClass;
|
||||
@ -198,6 +207,14 @@ def II_MADD_D : InstrItinClass;
|
||||
def II_MADD_S : InstrItinClass;
|
||||
def II_MADDF_D : InstrItinClass;
|
||||
def II_MADDF_S : InstrItinClass;
|
||||
def II_MAX_D : InstrItinClass;
|
||||
def II_MAX_S : InstrItinClass;
|
||||
def II_MAXA_D : InstrItinClass;
|
||||
def II_MAXA_S : InstrItinClass;
|
||||
def II_MIN_D : InstrItinClass;
|
||||
def II_MIN_S : InstrItinClass;
|
||||
def II_MINA_D : InstrItinClass;
|
||||
def II_MINA_S : InstrItinClass;
|
||||
def II_MFC0 : InstrItinClass;
|
||||
def II_MFC1 : InstrItinClass;
|
||||
def II_MFHC1 : InstrItinClass;
|
||||
@ -205,6 +222,7 @@ def II_MFC2 : InstrItinClass;
|
||||
def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
|
||||
def II_MOD : InstrItinClass;
|
||||
def II_MODU : InstrItinClass;
|
||||
def II_MOVE : InstrItinClass;
|
||||
def II_MOVF : InstrItinClass;
|
||||
def II_MOVF_D : InstrItinClass;
|
||||
def II_MOVF_S : InstrItinClass;
|
||||
@ -244,11 +262,14 @@ def II_NMADD_S : InstrItinClass;
|
||||
def II_NMSUB_D : InstrItinClass;
|
||||
def II_NMSUB_S : InstrItinClass;
|
||||
def II_NOR : InstrItinClass;
|
||||
def II_NOT : InstrItinClass;
|
||||
def II_OR : InstrItinClass;
|
||||
def II_ORI : InstrItinClass;
|
||||
def II_POP : InstrItinClass;
|
||||
def II_RDHWR : InstrItinClass;
|
||||
def II_RESTORE : InstrItinClass;
|
||||
def II_RINT_S : InstrItinClass;
|
||||
def II_RINT_D : InstrItinClass;
|
||||
def II_ROTR : InstrItinClass;
|
||||
def II_ROTRV : InstrItinClass;
|
||||
def II_ROUND : InstrItinClass;
|
||||
@ -267,6 +288,8 @@ def II_SDXC1 : InstrItinClass;
|
||||
def II_SEB : InstrItinClass;
|
||||
def II_SEH : InstrItinClass;
|
||||
def II_SELCCZ : InstrItinClass;
|
||||
def II_SELCCZ_D : InstrItinClass;
|
||||
def II_SELCCZ_S : InstrItinClass;
|
||||
def II_SEQ_SNE : InstrItinClass; // seq and sne
|
||||
def II_SEQI_SNEI : InstrItinClass; // seqi and snei
|
||||
def II_SH : InstrItinClass;
|
||||
@ -277,6 +300,8 @@ def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu
|
||||
def II_SLT_SLTU : InstrItinClass; // slt and sltu
|
||||
def II_SQRT_D : InstrItinClass;
|
||||
def II_SQRT_S : InstrItinClass;
|
||||
def II_SEL_D : InstrItinClass;
|
||||
def II_SEL_S : InstrItinClass;
|
||||
def II_SRA : InstrItinClass;
|
||||
def II_SRAV : InstrItinClass;
|
||||
def II_SRL : InstrItinClass;
|
||||
@ -293,6 +318,8 @@ def II_SWC2 : InstrItinClass;
|
||||
def II_SWC3 : InstrItinClass;
|
||||
def II_SWL : InstrItinClass;
|
||||
def II_SWLE : InstrItinClass;
|
||||
def II_SWM : InstrItinClass;
|
||||
def II_SWP : InstrItinClass;
|
||||
def II_SWR : InstrItinClass;
|
||||
def II_SWRE : InstrItinClass;
|
||||
def II_SWXC1 : InstrItinClass;
|
||||
@ -308,6 +335,10 @@ def II_LLE : InstrItinClass;
|
||||
def II_SCE : InstrItinClass;
|
||||
def II_TLBINV : InstrItinClass;
|
||||
def II_TLBINVF : InstrItinClass;
|
||||
def II_WRPGPR : InstrItinClass;
|
||||
def II_RDPGPR : InstrItinClass;
|
||||
def II_DVP : InstrItinClass;
|
||||
def II_EVP : InstrItinClass;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Mips Generic instruction itineraries.
|
||||
@ -370,6 +401,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_INS , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_MOVE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_MOVN_S , [InstrStage<1, [ALU]>]>,
|
||||
@ -377,6 +409,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_MOVT , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_MOVZ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_NOR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_NOT , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_OR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_POP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>,
|
||||
@ -394,6 +427,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_LHU , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LHUE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LW , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWM , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWP , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWPC , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWL , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWLE , [InstrStage<3, [ALU]>]>,
|
||||
@ -404,6 +439,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_LDL , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LDR , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LDPC , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LL , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LLD , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_RESTORE , [InstrStage<3, [ALU]>]>,
|
||||
@ -411,15 +447,18 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_SH , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SHE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SW , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWM , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SD , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SCD , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SELCCZ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SELCCZ_S , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SELCCZ_D , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SLTI_SLTIU , [InstrStage<1, [ALU]>]>,
|
||||
@ -433,12 +472,15 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_BC1T , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BC1TL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BC1CCZ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BC2CCZ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BCC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BCCC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BCCZ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BCCZAL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BCCZALS , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BCCZC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_CLASS_D , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_CLASS_S , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_IndirectBranchPseudo, [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_J , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JAL , [InstrStage<1, [ALU]>]>,
|
||||
@ -495,6 +537,14 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>,
|
||||
InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>,
|
||||
InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>,
|
||||
InstrItinData<II_MAX_D , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_MAX_S , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_MAXA_D , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_MAXA_S , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_MIN_S , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_MIN_D , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_MINA_S , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_MINA_D , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_MOD , [InstrStage<38, [IMULDIV]>]>,
|
||||
InstrItinData<II_MODU , [InstrStage<38, [IMULDIV]>]>,
|
||||
InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
|
||||
@ -533,6 +583,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_MOVZ_S , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_C_CC_S , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_C_CC_D , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_CMP_CC_S , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_CMP_CC_D , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_ADD_D , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_ADD_S , [InstrStage<4, [ALU]>]>,
|
||||
InstrItinData<II_SUB_D , [InstrStage<4, [ALU]>]>,
|
||||
@ -553,8 +605,12 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
|
||||
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
|
||||
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
|
||||
InstrItinData<II_RINT_D , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_RINT_S , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
|
||||
InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>,
|
||||
InstrItinData<II_SEL_D , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SEL_S , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_WSBH , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DLSA , [InstrStage<1, [ALU]>]>,
|
||||
@ -567,6 +623,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_LDXC1 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWXC1 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LUXC1 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWXS , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_SDC1 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDC2 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDC3 , [InstrStage<1, [ALU]>]>,
|
||||
@ -597,5 +654,9 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_TLBINV , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLBINVF , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LLE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_SCE , [InstrStage<1, [ALU]>]>
|
||||
InstrItinData<II_SCE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_WRPGPR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_RDPGPR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DVP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_EVP , [InstrStage<1, [ALU]>]>
|
||||
]>;
|
||||
|
||||
@ -154,13 +154,13 @@ entry:
|
||||
; MM32: lw $[[T3:[0-9]+]], 24($sp)
|
||||
; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
|
||||
; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]]
|
||||
; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
|
||||
; MM32: lw $[[T6:[0-9]+]], 16($sp)
|
||||
; MM32: lw $[[T7:[0-9]+]], 20($sp)
|
||||
; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
|
||||
; MM32: addu $[[T9:[0-9]+]], $5, $[[T8]]
|
||||
; MM32: lw $[[T10:[0-9]+]], 16($sp)
|
||||
; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]]
|
||||
; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T10]]
|
||||
; MM32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
|
||||
; MM32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]]
|
||||
; MM32: addu $[[T10:[0-9]+]], $5, $[[T9]]
|
||||
; MM32: sltu $[[T11:[0-6]+]], $[[T9]], $[[T7]]
|
||||
; MM32: addu $[[T12:[0-6]+]], $[[T11]], $[[T6]]
|
||||
; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]]
|
||||
; MM32: move $4, $[[T5]]
|
||||
; MM32: move $5, $[[T1]]
|
||||
|
||||
@ -131,13 +131,13 @@ entry:
|
||||
; GP64: and $2, $4, $6
|
||||
; GP64: and $3, $5, $7
|
||||
|
||||
; MM32: lw $[[T0:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 16($sp)
|
||||
; MM32: and16 $[[T1]], $4
|
||||
; MM32: and16 $[[T0]], $5
|
||||
; MM32: lw $[[T0:[0-9]+]], 32($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 28($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 24($sp)
|
||||
; MM32: and16 $[[T2]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; MM32: and16 $[[T2]], $4
|
||||
; MM32: and16 $[[T1]], $5
|
||||
; MM32: and16 $[[T0]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 36($sp)
|
||||
; MM32: and16 $[[T3]], $7
|
||||
|
||||
; MM64: and $2, $4, $6
|
||||
|
||||
@ -129,9 +129,9 @@ entry:
|
||||
; GP64: dsrav $2, $4, $5
|
||||
|
||||
; MMR3: srlv $[[T0:[0-9]+]], $5, $7
|
||||
; MMR3: sll16 $[[T1:[0-9]+]], $4, 1
|
||||
; MMR3: not16 $[[T2:[0-9]+]], $7
|
||||
; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
|
||||
; MMR3: not16 $[[T1:[0-9]+]], $7
|
||||
; MMR3: sll16 $[[T2:[0-9]+]], $4, 1
|
||||
; MMR3: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
|
||||
; MMR3: srav $[[T5:[0-9]+]], $4, $7
|
||||
; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
|
||||
@ -146,9 +146,9 @@ entry:
|
||||
; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]]
|
||||
; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]]
|
||||
; MMR6: srlv $[[T6:[0-9]+]], $5, $7
|
||||
; MMR6: sll16 $[[T7:[0-9]+]], $4, 1
|
||||
; MMR6: not16 $[[T8:[0-9]+]], $7
|
||||
; MMR6: sllv $[[T9:[0-9]+]], $[[T7]], $[[T8]]
|
||||
; MMR6: not16 $[[T7:[0-9]+]], $7
|
||||
; MMR6: sll16 $[[T8:[0-9]+]], $4, 1
|
||||
; MMR6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]]
|
||||
; MMR6: or16 $[[T10:[0-9]+]], $[[T6]]
|
||||
; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]]
|
||||
; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]]
|
||||
|
||||
@ -123,9 +123,9 @@ entry:
|
||||
; GP64: dsrlv $2, $4, $5
|
||||
|
||||
; MMR3: srlv $[[T0:[0-9]+]], $5, $7
|
||||
; MMR3: sll16 $[[T1:[0-9]+]], $4, 1
|
||||
; MMR3: not16 $[[T2:[0-9]+]], $7
|
||||
; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
|
||||
; MMR3: not16 $[[T1:[0-9]+]], $7
|
||||
; MMR3: sll16 $[[T2:[0-9]+]], $4, 1
|
||||
; MMR3: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
|
||||
; MMR3: srlv $[[T5:[0-9]+]], $4, $7
|
||||
; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
|
||||
@ -134,9 +134,9 @@ entry:
|
||||
; MMR3: movn $2, $[[T8]], $[[T6]]
|
||||
|
||||
; MMR6: srlv $[[T0:[0-9]+]], $5, $7
|
||||
; MMR6: sll16 $[[T1:[0-9]+]], $4, 1
|
||||
; MMR6: not16 $[[T2:[0-9]+]], $7
|
||||
; MMR6: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
|
||||
; MMR6: not16 $[[T1:[0-9]+]], $7
|
||||
; MMR6: sll16 $[[T2:[0-9]+]], $4, 1
|
||||
; MMR6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; MMR6: or16 $[[T4:[0-9]+]], $[[T0]]
|
||||
; MMR6: andi16 $[[T5:[0-9]+]], $7, 32
|
||||
; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]]
|
||||
|
||||
@ -247,7 +247,7 @@ entry:
|
||||
; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; 64R6: daddu $2, $[[T1]], $[[T0]]
|
||||
|
||||
; MM32: lw $25, %call16(__multi3)($2)
|
||||
; MM32: lw $25, %call16(__multi3)($16)
|
||||
|
||||
%r = mul i128 %a, %b
|
||||
ret i128 %r
|
||||
|
||||
@ -221,12 +221,12 @@ entry:
|
||||
; GP64: nor $2, $6, $4
|
||||
; GP64: nor $3, $7, $5
|
||||
|
||||
; MM32: lw $[[T0:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 16($sp)
|
||||
; MM32: nor $2, $[[T1]], $4
|
||||
; MM32: nor $3, $[[T0]], $5
|
||||
; MM32: lw $[[T2:[0-9]+]], 24($sp)
|
||||
; MM32: nor $4, $[[T2]], $6
|
||||
; MM32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; MM32: nor $2, $[[T2]], $4
|
||||
; MM32: nor $3, $[[T1]], $5
|
||||
; MM32: nor $4, $[[T0]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; MM32: nor $5, $[[T3]], $7
|
||||
|
||||
|
||||
@ -119,13 +119,13 @@ entry:
|
||||
; GP64: or $2, $4, $6
|
||||
; GP64: or $3, $5, $7
|
||||
|
||||
; MM32: lw $[[T0:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 16($sp)
|
||||
; MM32: or16 $[[T1]], $4
|
||||
; MM32: or16 $[[T0]], $5
|
||||
; MM32: lw $[[T0:[0-9]+]], 32($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 28($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 24($sp)
|
||||
; MM32: or16 $[[T2]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; MM32: or16 $[[T2]], $4
|
||||
; MM32: or16 $[[T1]], $5
|
||||
; MM32: or16 $[[T0]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 36($sp)
|
||||
; MM32: or16 $[[T3]], $7
|
||||
|
||||
; MM64: or $2, $4, $6
|
||||
|
||||
@ -188,7 +188,7 @@ entry:
|
||||
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
|
||||
; 64R6: ld $25, %call16(__divti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__divti3)($2)
|
||||
; MM32: lw $25, %call16(__divti3)($16)
|
||||
|
||||
; MM64: ld $25, %call16(__divti3)($2)
|
||||
|
||||
|
||||
@ -198,13 +198,13 @@ entry:
|
||||
; MM32R3: movn $3, $7, $[[T0]]
|
||||
|
||||
; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R6: lw $[[T1:[0-9]+]], 16($sp)
|
||||
; MM32R6: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; MM32R6: selnez $[[T3:[0-9]+]], $6, $[[T0]]
|
||||
; MM32R6: or $2, $[[T3]], $[[T2]]
|
||||
; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; MM32R6: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; MM32R6: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
|
||||
; MM32R6: or $2, $[[T1]], $[[T3]]
|
||||
; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
|
||||
; MM32R6: lw $[[T4:[0-9]+]], 20($sp)
|
||||
; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
|
||||
; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
|
||||
; MM32R6: or $3, $[[T6]], $[[T5]]
|
||||
|
||||
%r = select i1 %s, i64 %x, i64 %y
|
||||
|
||||
@ -139,9 +139,9 @@ entry:
|
||||
; GP64: dsllv $2, $4, $5
|
||||
|
||||
; MMR3: sllv $[[T0:[0-9]+]], $4, $7
|
||||
; MMR3: srl16 $[[T1:[0-9]+]], $5, 1
|
||||
; MMR3: not16 $[[T2:[0-9]+]], $7
|
||||
; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
|
||||
; MMR3: not16 $[[T1:[0-9]+]], $7
|
||||
; MMR3: srl16 $[[T2:[0-9]+]], $5, 1
|
||||
; MMR3: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
|
||||
; MMR3: sllv $[[T5:[0-9]+]], $5, $7
|
||||
; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
|
||||
@ -150,9 +150,9 @@ entry:
|
||||
; MMR3: movn $3, $[[T8]], $[[T6]]
|
||||
|
||||
; MMR6: sllv $[[T0:[0-9]+]], $4, $7
|
||||
; MMR6: srl16 $[[T1:[0-9]+]], $5, 1
|
||||
; MMR6: not16 $[[T2:[0-9]+]], $7
|
||||
; MMR6: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
|
||||
; MMR6: not16 $[[T1:[0-9]+]], $7
|
||||
; MMR6: srl16 $[[T2:[0-9]+]], $5, 1
|
||||
; MMR6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; MMR6: or16 $[[T4:[0-9]+]], $[[T0]]
|
||||
; MMR6: andi16 $[[T5:[0-9]+]], $7, 32
|
||||
; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]]
|
||||
|
||||
@ -180,7 +180,7 @@ entry:
|
||||
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
|
||||
; 64R6: ld $25, %call16(__modti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__modti3)($2)
|
||||
; MM32: lw $25, %call16(__modti3)($16)
|
||||
|
||||
; MM64: ld $25, %call16(__modti3)($2)
|
||||
|
||||
|
||||
@ -134,16 +134,16 @@ entry:
|
||||
; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
|
||||
; GP32-MM: lw $[[T3:[0-9]+]], 16($sp)
|
||||
; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]]
|
||||
; GP32-MM: lw $[[T5:[0-9]+]], 24($sp)
|
||||
; GP32-MM: lw $[[T4:[0-9]+]], 28($sp)
|
||||
; GP32-MM: subu $[[T1]], $7, $[[T4]]
|
||||
; GP32-MM: subu $[[T3]], $[[T5:[0-9]+]], $[[T3]]
|
||||
; GP32-MM: lw $[[T5]], 24($sp)
|
||||
; GP32-MM: subu $[[T3]], $4, $[[T3]]
|
||||
; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
|
||||
; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]]
|
||||
; GP32-MM: subu $[[T0]], $5, $[[T0]]
|
||||
; GP32-MM: sltu $[[T2]], $7, $[[T4]]
|
||||
; GP32-MM: addu $[[T5]], $[[T2]], $[[T5]]
|
||||
; GP32-MM: subu $[[T5]], $6, $[[T5]]
|
||||
; GP32-MM: sltu $[[T7:[0-9]+]], $7, $[[T4]]
|
||||
; GP32-MM: addu $[[T8:[0-8]+]], $[[T7]], $[[T5]]
|
||||
; GP32-MM: subu $[[T9:[0-9]+]], $6, $[[T8]]
|
||||
; GP32-MM: move $[[T2]], $[[T1]]
|
||||
|
||||
; GP64: dsubu $3, $5, $7
|
||||
|
||||
@ -152,7 +152,7 @@ entry:
|
||||
; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
|
||||
; 64-R6: ld $25, %call16(__udivti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__udivti3)($2)
|
||||
; MM32: lw $25, %call16(__udivti3)($16)
|
||||
|
||||
; MM64: ld $25, %call16(__udivti3)($2)
|
||||
|
||||
|
||||
@ -208,7 +208,7 @@ entry:
|
||||
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
|
||||
; 64R6: ld $25, %call16(__umodti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__umodti3)($2)
|
||||
; MM32: lw $25, %call16(__umodti3)($16)
|
||||
|
||||
; MM64: ld $25, %call16(__umodti3)($2)
|
||||
|
||||
|
||||
@ -129,13 +129,13 @@ entry:
|
||||
; GP64: xor $2, $4, $6
|
||||
; GP64: xor $3, $5, $7
|
||||
|
||||
; MM32: lw $[[T0:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 16($sp)
|
||||
; MM32: xor16 $[[T1]], $4
|
||||
; MM32: xor16 $[[T0]], $5
|
||||
; MM32: lw $[[T0:[0-9]+]], 32($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 28($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 24($sp)
|
||||
; MM32: xor16 $[[T2]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; MM32: xor16 $[[T2]], $4
|
||||
; MM32: xor16 $[[T1]], $5
|
||||
; MM32: xor16 $[[T0]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 36($sp)
|
||||
; MM32: xor16 $[[T3]], $7
|
||||
|
||||
; MM64: xor $2, $4, $6
|
||||
|
||||
Loading…
Reference in New Issue
Block a user