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GlobalISel: add a G_PHI instruction to give phis a type.

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They're another source of generic vregs, which are going to need a type on the
definition when we remove the register width from MachineRegisterInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280412 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2016-09-01 20:45:41 +00:00
parent 2ae7de27f7
commit 3b190749fe
7 changed files with 25 additions and 4 deletions
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5
include/llvm/CodeGen/MachineInstr.h
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@ -793,7 +793,10 @@ public:
&& getOperand(1).isImm();
}
bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
bool isPHI() const {
return getOpcode() == TargetOpcode::PHI ||
getOpcode() == TargetOpcode::G_PHI;
}
bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }

7
include/llvm/Target/GenericOpcodes.td
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@ -415,6 +415,13 @@ def G_INTRINSIC_W_SIDE_EFFECTS : Instruction {
let mayStore = 1;
}
// PHI node bearing an LLT.
def G_PHI : Instruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins variable_ops);
let hasSideEffects = 0;
}
//------------------------------------------------------------------------------
// Branches.
//------------------------------------------------------------------------------

3
include/llvm/Target/TargetOpcodes.def
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@ -336,6 +336,9 @@ HANDLE_TARGET_OPCODE(G_UITOFP)
/// Generic type specifier for untyped registers.
HANDLE_TARGET_OPCODE(G_TYPE)
/// Generic PHI node (so that the type of the vreg can be set).
HANDLE_TARGET_OPCODE(G_PHI)
/// Generic BRANCH instruction. This is an unconditional branch.
HANDLE_TARGET_OPCODE(G_BR)

2
lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -405,7 +405,7 @@ bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
bool IRTranslator::translatePHI(const User &U) {
const PHINode &PI = cast<PHINode>(U);
MachineInstrBuilder MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, LLT{*U.getType()});
MIB.addDef(getOrCreateVReg(PI));
PendingPHIs.emplace_back(&PI, MIB.getInstr());

4
lib/CodeGen/GlobalISel/MachineLegalizer.cpp
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@ -30,8 +30,10 @@ MachineLegalizer::MachineLegalizer() : TablesInitialized(false) {
DefaultActions[TargetOpcode::G_ANYEXT] = Legal;
DefaultActions[TargetOpcode::G_TRUNC] = Legal;
// G_TYPE is essentially an annotated COPY so it's always legal.
// G_TYPE and G_PHI are essentially an annotated COPY/PHI instructions so
// they're always legal.
DefaultActions[TargetOpcode::G_TYPE] = Legal;
DefaultActions[TargetOpcode::G_PHI] = Legal;
DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;

6
lib/Target/AArch64/AArch64InstructionSelector.cpp
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@ -235,6 +235,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
return true;
}
case TargetOpcode::G_PHI: {
I.setDesc(TII.get(TargetOpcode::PHI));
I.removeTypes();
return true;
}
case TargetOpcode::G_FRAME_INDEX: {
// allocas and G_FRAME_INDEX are only supported in addrspace(0).
if (I.getType() != LLT::pointer(0)) {

2
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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@ -325,7 +325,7 @@ define void @intrinsics(i32 %cur, i32 %bits) {
; CHECK: [[FALSE]]:
; CHECK: [[RES2:%[0-9]+]](32) = G_LOAD { s32, p0 }
; CHECK: [[RES:%[0-9]+]](32) = PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
; CHECK: [[RES:%[0-9]+]](32) = G_PHI s32 [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
; CHECK: %w0 = COPY [[RES]]
define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
br i1 %tst, label %true, label %false