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Add support for FMA to WidenVectorResult.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162893 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -625,6 +625,7 @@ private:
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SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
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SDValue WidenVecRes_VSETCC(SDNode* N);
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SDValue WidenVecRes_Ternary(SDNode *N);
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SDValue WidenVecRes_Binary(SDNode *N);
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SDValue WidenVecRes_Convert(SDNode *N);
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SDValue WidenVecRes_POWI(SDNode *N);
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@ -1366,6 +1366,9 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::FTRUNC:
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Res = WidenVecRes_Unary(N);
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break;
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case ISD::FMA:
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Res = WidenVecRes_Ternary(N);
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break;
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}
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// If Res is null, the sub-method took care of registering the result.
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@ -1373,6 +1376,16 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
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SetWidenedVector(SDValue(N, ResNo), Res);
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}
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SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
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// Ternary op widening.
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DebugLoc dl = N->getDebugLoc();
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EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
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SDValue InOp1 = GetWidenedVector(N->getOperand(0));
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SDValue InOp2 = GetWidenedVector(N->getOperand(1));
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SDValue InOp3 = GetWidenedVector(N->getOperand(2));
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return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
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}
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SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
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// Binary op widening.
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unsigned Opcode = N->getOpcode();
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