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Implement select handling for ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -128,6 +128,7 @@ class ARMFastISel : public FastISel {
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virtual bool SelectFPToSI(const Instruction *I);
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virtual bool SelectSDiv(const Instruction *I);
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virtual bool SelectCall(const Instruction *I);
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virtual bool SelectSelect(const Instruction *I);
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// Utility routines.
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private:
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@ -1063,6 +1064,34 @@ bool ARMFastISel::SelectFPToSI(const Instruction *I) {
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return true;
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}
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bool ARMFastISel::SelectSelect(const Instruction *I) {
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EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
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return false;
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// Things need to be register sized for register moves.
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if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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unsigned CondReg = getRegForValue(I->getOperand(0));
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if (CondReg == 0) return false;
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unsigned Op1Reg = getRegForValue(I->getOperand(1));
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if (Op1Reg == 0) return false;
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unsigned Op2Reg = getRegForValue(I->getOperand(2));
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if (Op2Reg == 0) return false;
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unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
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.addReg(CondReg).addImm(1));
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unsigned ResultReg = createResultReg(RC);
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unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
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.addReg(Op1Reg).addReg(Op2Reg)
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.addImm(ARMCC::EQ).addReg(ARM::CPSR);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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bool ARMFastISel::SelectSDiv(const Instruction *I) {
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EVT VT;
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const Type *Ty = I->getType();
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@ -1490,6 +1519,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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return SelectSDiv(I);
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case Instruction::Call:
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return SelectCall(I);
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case Instruction::Select:
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return SelectSelect(I);
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default: break;
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}
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return false;
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