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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36203 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -476,3 +476,46 @@ More LSR enhancements possible:
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in a load / store.
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in a load / store.
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2. Allow iv reuse even when a type conversion is required. For example, i8
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2. Allow iv reuse even when a type conversion is required. For example, i8
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and i32 load / store addressing modes are identical.
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and i32 load / store addressing modes are identical.
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//===---------------------------------------------------------------------===//
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This:
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int foo(int a, int b, int c, int d) {
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long long acc = (long long)a * (long long)b;
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acc += (long long)c * (long long)d;
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return (int)(acc >> 32);
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}
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Should compile to use SMLAL (Signed Multiply Accumulate Long) which multiplies
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two signed 32-bit values to produce a 64-bit value, and accumulates this with
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a 64-bit value.
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We currently get this with v6:
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_foo:
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mul r12, r1, r0
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smmul r1, r1, r0
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smmul r0, r3, r2
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mul r3, r3, r2
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adds r3, r3, r12
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adc r0, r0, r1
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bx lr
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and this with v4:
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_foo:
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stmfd sp!, {r7, lr}
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mov r7, sp
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mul r12, r1, r0
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smull r0, r1, r1, r0
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smull lr, r0, r3, r2
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mul r3, r3, r2
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adds r3, r3, r12
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adc r0, r0, r1
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ldmfd sp!, {r7, pc}
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This apparently occurs in real code.
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//===---------------------------------------------------------------------===//
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