diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 749022ddb49..cf461a1d1b4 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -610,7 +610,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) { Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io; } else if (LoadedVT == MVT::i8) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib; + Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::L2_loadrb_pi; else Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io; } else diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 01952990bad..71c92a5e8b4 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -694,7 +694,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::POST_LDriuh: return isShiftedInt<4,1>(MI->getOperand(3).getImm()); - case Hexagon::POST_LDrib: + case Hexagon::L2_loadrb_pi: case Hexagon::POST_LDriub: return isInt<4>(MI->getOperand(3).getImm()); @@ -1363,8 +1363,8 @@ isConditionalLoad (const MachineInstr* MI) const { case Hexagon::POST_LDriw_cNotPt : case Hexagon::POST_LDrih_cPt : case Hexagon::POST_LDrih_cNotPt : - case Hexagon::POST_LDrib_cPt : - case Hexagon::POST_LDrib_cNotPt : + case Hexagon::L2_ploadrbt_pi : + case Hexagon::L2_ploadrbf_pi : case Hexagon::POST_LDriuh_cPt : case Hexagon::POST_LDriuh_cNotPt : case Hexagon::POST_LDriub_cPt : diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 2204de12233..6070a1fd076 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -1599,6 +1599,106 @@ def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))), //===----------------------------------------------------------------------===// // Post increment load //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// Template class for non-predicated post increment loads with immediate offset. +//===----------------------------------------------------------------------===// +let hasSideEffects = 0, addrMode = PostInc in +class T_load_pi MajOp > + : LDInstPI <(outs RC:$dst, IntRegs:$dst2), + (ins IntRegs:$src1, ImmOp:$offset), + "$dst = "#mnemonic#"($src1++#$offset)" , + [], + "$src1 = $dst2" > , + PredNewRel { + bits<5> dst; + bits<5> src1; + bits<7> offset; + bits<4> offsetBits; + + string ImmOpStr = !cast(ImmOp); + let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, + !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, + !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, + /* s4_0Imm */ offset{3-0}))); + let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); + + let IClass = 0b1001; + + let Inst{27-25} = 0b101; + let Inst{24-21} = MajOp; + let Inst{20-16} = src1; + let Inst{13-12} = 0b00; + let Inst{8-5} = offsetBits; + let Inst{4-0} = dst; + } + +//===----------------------------------------------------------------------===// +// Template class for predicated post increment loads with immediate offset. +//===----------------------------------------------------------------------===// +let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in +class T_pload_pi MajOp, bit isPredNot, bit isPredNew > + : LDInst <(outs RC:$dst, IntRegs:$dst2), + (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), + !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + ") ")#"$dst = "#mnemonic#"($src2++#$offset)", + [] , + "$src2 = $dst2" > , + PredNewRel { + bits<5> dst; + bits<2> src1; + bits<5> src2; + bits<7> offset; + bits<4> offsetBits; + + let isPredicatedNew = isPredNew; + let isPredicatedFalse = isPredNot; + + string ImmOpStr = !cast(ImmOp); + let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, + !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, + !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, + /* s4_0Imm */ offset{3-0}))); + let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); + + let IClass = 0b1001; + + let Inst{27-25} = 0b101; + let Inst{24-21} = MajOp; + let Inst{20-16} = src2; + let Inst{13} = 0b1; + let Inst{12} = isPredNew; + let Inst{11} = isPredNot; + let Inst{10-9} = src1; + let Inst{8-5} = offsetBits; + let Inst{4-0} = dst; + } + +//===----------------------------------------------------------------------===// +// Multiclass for post increment loads with immediate offset. +//===----------------------------------------------------------------------===// + +multiclass LD_PostInc MajOp> { + let BaseOpcode = "POST_"#BaseOp in { + let isPredicable = 1 in + def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>; + + // Predicated + def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>; + def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>; + + // Predicated new + def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>; + def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>; + } +} + +// post increment byte loads with immediate offset +let accessSize = ByteAccess, isCodeGenOnly = 0 in { + defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>; +} multiclass LD_PostInc_Pbase { @@ -1621,7 +1721,7 @@ multiclass LD_PostInc_Pred { let BaseOpcode = "POST_"#BaseOp in { @@ -1640,17 +1740,15 @@ multiclass LD_PostInc, + defm POST_LDriub : LD_PostInc2<"memub", "LDriub", IntRegs, s4_0Imm>, PredNewRel; - defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>, + defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>, PredNewRel; - defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>, + defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>, PredNewRel; - defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>, + defm POST_LDriw : LD_PostInc2<"memw", "LDriw", IntRegs, s4_2Imm>, PredNewRel; - defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>, - PredNewRel; - defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>, + defm POST_LDrid : LD_PostInc2<"memd", "LDrid", DoubleRegs, s4_3Imm>, PredNewRel; } diff --git a/test/MC/Disassembler/Hexagon/ld.txt b/test/MC/Disassembler/Hexagon/ld.txt index 26f60613a6c..c3d6556e59b 100644 --- a/test/MC/Disassembler/Hexagon/ld.txt +++ b/test/MC/Disassembler/Hexagon/ld.txt @@ -10,6 +10,7 @@ 0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x47 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17:16 = memd(r21 + #24) + 0xf1 0xc3 0x15 0x91 # CHECK: r17 = memb(r21 + #31) 0x91 0xdd 0x15 0x41 @@ -22,10 +23,14 @@ 0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44) + 0xf1 0xc3 0x55 0x91 # CHECK: r17 = memh(r21 + #62) + 0xf1 0xc3 0x35 0x91 # CHECK: r17 = memub(r21 + #31) +0xb1 0xc0 0x15 0x9b +# CHECK: r17 = memb(r21++#5) 0xf1 0xdb 0x35 0x41 # CHECK: if (p3) r17 = memub(r21 + #31) 0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43 @@ -36,6 +41,17 @@ 0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31) +0xb1 0xe6 0x15 0x9b +# CHECK: if (p3) r17 = memb(r21++#5) +0xb1 0xee 0x15 0x9b +# CHECK: if (!p3) r17 = memb(r21++#5) +0x03 0x40 0x45 0x85 0xb1 0xf6 0x15 0x9b +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memb(r21++#5) +0x03 0x40 0x45 0x85 0xb1 0xfe 0x15 0x9b +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5) + 0xb1 0xc2 0x75 0x91 # CHECK: r17 = memuh(r21 + #42) 0xb1 0xda 0x75 0x41 @@ -48,6 +64,7 @@ 0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42) + 0xb1 0xc2 0x95 0x91 # CHECK: r17 = memw(r21 + #84) 0xb1 0xda 0x95 0x41