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LLVM currently represents floating-point negation as -0.0 - x. Fix
FastISel to recognize this pattern and emit a floating-point negation using xor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80963 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -300,6 +300,8 @@ protected:
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private:
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bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
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bool SelectFNeg(User *I);
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bool SelectGetElementPtr(User *I);
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bool SelectCall(User *I);
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@ -608,6 +608,26 @@ FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
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MBB->addSuccessor(MSucc);
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}
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/// SelectFNeg - Emit an FNeg operation.
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///
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bool
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FastISel::SelectFNeg(User *I) {
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unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
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if (OpReg == 0) return false;
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// Twiddle the sign bit with xor.
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EVT VT = TLI.getValueType(I->getType());
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if (VT.getSizeInBits() > 64) return false;
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unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISD::XOR, OpReg,
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UINT64_C(1) << (VT.getSizeInBits()-1),
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VT.getSimpleVT());
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if (ResultReg == 0)
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return false;
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UpdateValueMap(I, ResultReg);
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return true;
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}
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bool
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FastISel::SelectOperator(User *I, unsigned Opcode) {
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switch (Opcode) {
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@ -618,6 +638,9 @@ FastISel::SelectOperator(User *I, unsigned Opcode) {
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case Instruction::Sub:
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return SelectBinaryOp(I, ISD::SUB);
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case Instruction::FSub:
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// FNeg is currently represented in LLVM IR as a special case of FSub.
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if (BinaryOperator::isFNeg(I))
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return SelectFNeg(I);
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return SelectBinaryOp(I, ISD::FSUB);
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case Instruction::Mul:
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return SelectBinaryOp(I, ISD::MUL);
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15
test/CodeGen/X86/fast-isel-fneg.ll
Normal file
15
test/CodeGen/X86/fast-isel-fneg.ll
Normal file
@ -0,0 +1,15 @@
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; RUN: llvm-as < %s | llc -fast-isel -march=x86-64 | FileCheck %s
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; CHECK: doo:
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; CHECK: xorpd
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define double @doo(double %x) nounwind {
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%y = fsub double -0.0, %x
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ret double %y
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}
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; CHECK: foo:
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; CHECK: xorps
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define float @foo(float %x) nounwind {
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%y = fsub float -0.0, %x
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ret float %y
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}
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