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teach isel about comparison with constants and zero extending bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19853 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
9437bb6d27
commit
3d65d31e20
@ -38,31 +38,29 @@ namespace {
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public:
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AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
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// Set up the TargetLowering object.
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//I am having problems with shr n ubyte 1
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setShiftAmountType(MVT::i64); //are these needed?
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setSetCCResultType(MVT::i64); //are these needed?
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addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
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addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
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addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Expand); //Should this be Promote? Chris?
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setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand); //Should this be Promote? Chris?
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setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); //Should this be Promote? Chris?
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setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
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setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); //what is the sign expansion of 1? 1 or -1?
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// setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
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// setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
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setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
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setOperationAction(ISD::SREM, MVT::f32, Expand);
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setOperationAction(ISD::SREM, MVT::f64, Expand);
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setOperationAction(ISD::FP_TO_SINT , MVT::f32 , Promote);
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computeRegisterProperties();
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computeRegisterProperties();
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// addLegalFPImmediate(+0.0); // FLD0
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// addLegalFPImmediate(+1.0); // FLD1
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@ -366,7 +364,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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BuildMI(BB, Alpha::LDWU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i8:
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case MVT::i1: //FIXME: DAG does not expand i8??
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BuildMI(BB, Alpha::LDBU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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}
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@ -393,12 +390,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case MVT::i32:
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BuildMI(BB, Alpha::LDL, 2, Result).addImm(0).addReg(Tmp1);
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break;
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// case MVT::i16:
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// BuildMI(BB, Alpha::LDW, 2, Result).addImm(0).addReg(Tmp1);
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// break;
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// case MVT::i8:
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// BuildMI(BB, Alpha::LDB, 2, Result).addImm(0).addReg(Tmp1);
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// break;
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}
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break;
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}
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@ -520,29 +511,31 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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case ISD::SIGN_EXTEND:
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abort();
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case ISD::SIGN_EXTEND_INREG:
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{
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Tmp1 = SelectExpr(N.getOperand(0));
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MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
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//std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
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switch(MVN->getExtraValueType())
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{
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default:
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Node->dump();
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assert(0 && "Sign Extend InReg not there yet");
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break;
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case MVT::i32:
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{
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BuildMI(BB, Alpha::ADDLi, 2, Result).addReg(Tmp1).addImm(0);
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break;
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}
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case MVT::i16:
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BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
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break;
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case MVT::i8:
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BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
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break;
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}
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{
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default:
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Node->dump();
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assert(0 && "Sign Extend InReg not there yet");
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break;
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case MVT::i32:
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{
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BuildMI(BB, Alpha::ADDLi, 2, Result).addReg(Tmp1).addImm(0);
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break;
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}
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case MVT::i16:
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BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
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break;
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case MVT::i8:
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BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
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break;
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}
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return Result;
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}
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case ISD::ZERO_EXTEND_INREG:
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@ -551,75 +544,103 @@ unsigned ISel::SelectExpr(SDOperand N) {
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MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
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//std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
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switch(MVN->getExtraValueType())
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{
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default:
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Node->dump();
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assert(0 && "Zero Extend InReg not there yet");
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break;
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case MVT::i32: Tmp2 = 0xf0; break;
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case MVT::i16: Tmp2 = 0xfc; break;
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case MVT::i8: Tmp2 = 0xfe; break;
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}
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{
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default:
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Node->dump();
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assert(0 && "Zero Extend InReg not there yet");
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break;
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case MVT::i32: Tmp2 = 0xf0; break;
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case MVT::i16: Tmp2 = 0xfc; break;
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case MVT::i8: Tmp2 = 0xfe; break;
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case MVT::i1: //handle this one special
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BuildMI(BB, Alpha::ANDi, 2, Result).addReg(Tmp1).addImm(1);
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return Result;
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}
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BuildMI(BB, Alpha::ZAPi, 2, Result).addReg(Tmp1).addImm(Tmp2);
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return Result;
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return Result;
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}
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case ISD::SETCC:
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
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if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
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switch (SetCC->getCondition()) {
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default: Node->dump(); assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ:
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BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case ISD::SETGT:
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BuildMI(BB, Alpha::CMPLT, 2, Result).addReg(Tmp2).addReg(Tmp1);
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break;
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case ISD::SETGE:
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BuildMI(BB, Alpha::CMPLE, 2, Result).addReg(Tmp2).addReg(Tmp1);
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break;
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case ISD::SETLT:
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BuildMI(BB, Alpha::CMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case ISD::SETLE:
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BuildMI(BB, Alpha::CMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case ISD::SETNE:
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{
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unsigned Tmp3 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp3).addReg(Alpha::R31);
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break;
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}
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case ISD::SETULT:
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BuildMI(BB, Alpha::CMPULT, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case ISD::SETUGT:
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BuildMI(BB, Alpha::CMPULT, 2, Result).addReg(Tmp2).addReg(Tmp1);
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break;
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case ISD::SETULE:
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BuildMI(BB, Alpha::CMPULE, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case ISD::SETUGE:
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BuildMI(BB, Alpha::CMPULE, 2, Result).addReg(Tmp2).addReg(Tmp1);
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break;
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}
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{
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if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
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if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
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bool isConst1 = false;
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bool isConst2 = false;
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int dir;
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//Tmp1 = SelectExpr(N.getOperand(0));
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if(N.getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
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isConst1 = true;
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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isConst2 = true;
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switch (SetCC->getCondition()) {
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default: Node->dump(); assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ: Opc = Alpha::CMPEQ; dir=0; break;
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case ISD::SETLT: Opc = isConst2 ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
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case ISD::SETLE: Opc = isConst2 ? Alpha::CMPLEi : Alpha::CMPLE; dir = 1; break;
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case ISD::SETGT: Opc = isConst1 ? Alpha::CMPLTi : Alpha::CMPLT; dir = 2; break;
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case ISD::SETGE: Opc = isConst1 ? Alpha::CMPLEi : Alpha::CMPLE; dir = 2; break;
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case ISD::SETULT: Opc = isConst2 ? Alpha::CMPULTi : Alpha::CMPULT; dir = 1; break;
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case ISD::SETUGT: Opc = isConst1 ? Alpha::CMPULTi : Alpha::CMPULT; dir = 2; break;
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case ISD::SETULE: Opc = isConst2 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
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case ISD::SETUGE: Opc = isConst1 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 2; break;
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case ISD::SETNE:
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std::cerr << "Alpha does not have a setne.\n";
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abort();
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}
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if (dir == 1) {
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isConst2) {
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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} else {
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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} else if (dir == 2) {
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Tmp1 = SelectExpr(N.getOperand(1));
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if (isConst2) {
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Tmp2 = cast<ConstantSDNode>(N.getOperand(0))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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} else {
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Tmp2 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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} else { //dir == 0
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if (isConst1) {
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Tmp1 = cast<ConstantSDNode>(N.getOperand(0))->getValue();
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CMPEQi, 2, Result).addReg(Tmp2).addImm(Tmp1);
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} else if (isConst2) {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Alpha::CMPEQi, 2, Result).addReg(Tmp1).addImm(Tmp2);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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}
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}
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else
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{
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Node->dump();
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assert(0 && "only integer");
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}
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}
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else
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{
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Node->dump();
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assert(0 && "only integer");
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}
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{
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Node->dump();
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assert(0 && "Not a setcc in setcc");
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}
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return Result;
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}
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else
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{
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Node->dump();
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assert(0 && "Not a setcc in setcc");
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}
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return Result;
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case ISD::CopyFromReg:
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{
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if (Result == 1)
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@ -113,18 +113,6 @@ def BIC : OForm< 0x11, 0x08, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "BIC $RA,$
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def BICi : OFormL<0x11, 0x08, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "BIC $RA,$L,$RC">; //Bit clear
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def BIS : OForm< 0x11, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "bis $RA,$RB,$RC">; //Logical sum
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def BISi : OFormL<0x11, 0x20, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "bis $RA,$L,$RC">; //Logical sum
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def CMPBGE : OForm< 0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPBGE $RA,$RB,$RC">; //Compare byte
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def CMPBGEi : OFormL<0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPBGE $RA,$L,$RC">; //Compare byte
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def CMPEQ : OForm< 0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPEQ $RA,$RB,$RC">; //Compare signed quadword equal
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def CMPEQi : OFormL<0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPEQ $RA,$L,$RC">; //Compare signed quadword equal
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def CMPLE : OForm< 0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPLE $RA,$RB,$RC">; //Compare signed quadword less than or equal
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def CMPLEi : OFormL<0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPLE $RA,$L,$RC">; //Compare signed quadword less than or equal
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def CMPLT : OForm< 0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPLT $RA,$RB,$RC">; //Compare signed quadword less than
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def CMPLTi : OFormL<0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPLT $RA,$L,$RC">; //Compare signed quadword less than
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def CMPULE : OForm< 0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPULE $RA,$RB,$RC">; //Compare unsigned quadword less than or equal
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def CMPULEi : OFormL<0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPULE $RA,$L,$RC">; //Compare unsigned quadword less than or equal
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def CMPULT : OForm< 0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPULT $RA,$RB,$RC">; //Compare unsigned quadword less than
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def CMPULTi : OFormL<0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPULT $RA,$L,$RC">; //Compare unsigned quadword less than
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def CTLZ : OForm< 0x1C, 0x32, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CTLZ $RA,$RB,$RC">; //Count leading zero
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def CTLZi : OFormL<0x1C, 0x32, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CTLZ $RA,$L,$RC">; //Count leading zero
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def CTPOP : OForm< 0x1C, 0x30, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CTPOP $RA,$RB,$RC">; //Count population
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@ -222,6 +210,21 @@ def ZAPi : OFormL<0x12, 0x30, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "ZAP $RA,$
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def ZAPNOT : OForm< 0x12, 0x31, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "ZAPNOT $RA,$RB,$RC">; //Zero bytes not
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def ZAPNOTi : OFormL<0x12, 0x31, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "ZAPNOT $RA,$L,$RC">; //Zero bytes not
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//Comparison, int
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def CMPBGE : OForm< 0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPBGE $RA,$RB,$RC">; //Compare byte
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def CMPBGEi : OFormL<0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPBGE $RA,$L,$RC">; //Compare byte
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def CMPEQ : OForm< 0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPEQ $RA,$RB,$RC">; //Compare signed quadword equal
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def CMPEQi : OFormL<0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPEQ $RA,$L,$RC">; //Compare signed quadword equal
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def CMPLE : OForm< 0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPLE $RA,$RB,$RC">; //Compare signed quadword less than or equal
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def CMPLEi : OFormL<0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPLE $RA,$L,$RC">; //Compare signed quadword less than or equal
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def CMPLT : OForm< 0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPLT $RA,$RB,$RC">; //Compare signed quadword less than
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def CMPLTi : OFormL<0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPLT $RA,$L,$RC">; //Compare signed quadword less than
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def CMPULE : OForm< 0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPULE $RA,$RB,$RC">; //Compare unsigned quadword less than or equal
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def CMPULEi : OFormL<0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPULE $RA,$L,$RC">; //Compare unsigned quadword less than or equal
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def CMPULT : OForm< 0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPULT $RA,$RB,$RC">; //Compare unsigned quadword less than
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def CMPULTi : OFormL<0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPULT $RA,$L,$RC">; //Compare unsigned quadword less than
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//There are in the Multimedia extentions, so let's not use them yet
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def MAXSB8 : OForm<0x1C, 0x3E, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
|
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def MAXSW4 : OForm< 0x1C, 0x3F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
|
||||
|
||||
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Reference in New Issue
Block a user