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[X86][AVX512] Dropped avx512 VPSLLDQ/VPSRLDQ intrinsics
Auto-upgrade to generic shuffles like sse/avx2 implementations now that we can lower to VPSLLDQ/VPSRLDQ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272308 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -223,6 +223,8 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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Name.startswith("x86.sse2.psrl.dq") ||
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Name.startswith("x86.avx2.psll.dq") ||
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Name.startswith("x86.avx2.psrl.dq") ||
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Name.startswith("x86.avx512.psll.dq") ||
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Name.startswith("x86.avx512.psrl.dq") ||
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Name == "x86.sse41.pblendw" ||
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Name.startswith("x86.sse41.blendp") ||
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Name.startswith("x86.avx.blend.p") ||
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@ -333,7 +335,7 @@ bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) {
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return false;
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}
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// Handles upgrading SSE2 and AVX2 PSLLDQ intrinsics by converting them
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// Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them
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// to byte shuffles.
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static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, LLVMContext &C,
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Value *Op, unsigned Shift) {
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@ -350,8 +352,8 @@ static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, LLVMContext &C,
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// If shift is less than 16, emit a shuffle to move the bytes. Otherwise,
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// we'll just return the zero vector.
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if (Shift < 16) {
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int Idxs[32];
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// 256-bit version is split into two 16-byte lanes.
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int Idxs[64];
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// 256/512-bit version is split into 2/4 16-byte lanes.
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for (unsigned l = 0; l != NumElts; l += 16)
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for (unsigned i = 0; i != 16; ++i) {
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unsigned Idx = NumElts + i - Shift;
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@ -414,7 +416,7 @@ static Value *UpgradeX86PALIGNRIntrinsics(IRBuilder<> &Builder, LLVMContext &C,
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return Builder.CreateSelect(Mask, Align, Passthru);
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}
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// Handles upgrading SSE2 and AVX2 PSRLDQ intrinsics by converting them
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// Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them
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// to byte shuffles.
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static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, LLVMContext &C,
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Value *Op,
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@ -432,8 +434,8 @@ static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, LLVMContext &C,
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// If shift is less than 16, emit a shuffle to move the bytes. Otherwise,
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// we'll just return the zero vector.
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if (Shift < 16) {
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int Idxs[32];
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// 256-bit version is split into two 16-byte lanes.
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int Idxs[64];
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// 256/512-bit version is split into 2/4 16-byte lanes.
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for (unsigned l = 0; l != NumElts; l += 16)
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for (unsigned i = 0; i != 16; ++i) {
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unsigned Idx = i + Shift;
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@ -792,13 +794,15 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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Rep = UpgradeX86PSRLDQIntrinsics(Builder, C, CI->getArgOperand(0),
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Shift / 8); // Shift is in bits.
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} else if (Name == "llvm.x86.sse2.psll.dq.bs" ||
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Name == "llvm.x86.avx2.psll.dq.bs") {
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// 128/256-bit shift left specified in bytes.
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Name == "llvm.x86.avx2.psll.dq.bs" ||
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Name == "llvm.x86.avx512.psll.dq.512") {
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// 128/256/512-bit shift left specified in bytes.
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unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
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Rep = UpgradeX86PSLLDQIntrinsics(Builder, C, CI->getArgOperand(0), Shift);
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} else if (Name == "llvm.x86.sse2.psrl.dq.bs" ||
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Name == "llvm.x86.avx2.psrl.dq.bs") {
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// 128/256-bit shift right specified in bytes.
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Name == "llvm.x86.avx2.psrl.dq.bs" ||
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Name == "llvm.x86.avx512.psrl.dq.512") {
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// 128/256/512-bit shift right specified in bytes.
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unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
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Rep = UpgradeX86PSRLDQIntrinsics(Builder, C, CI->getArgOperand(0), Shift);
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} else if (Name == "llvm.x86.sse41.pblendw" ||
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@ -2002,8 +2002,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_pbroadcastw_512, INTR_TYPE_1OP_MASK,
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X86ISD::VBROADCAST, 0),
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X86_INTRINSIC_DATA(avx512_psad_bw_512, INTR_TYPE_2OP, X86ISD::PSADBW, 0),
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X86_INTRINSIC_DATA(avx512_psll_dq_512, INTR_TYPE_2OP_IMM8, X86ISD::VSHLDQ, 0),
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X86_INTRINSIC_DATA(avx512_psrl_dq_512, INTR_TYPE_2OP_IMM8, X86ISD::VSRLDQ, 0),
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X86_INTRINSIC_DATA(avx512_ptestm_b_128, CMP_MASK, X86ISD::TESTM, 0),
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X86_INTRINSIC_DATA(avx512_ptestm_b_256, CMP_MASK, X86ISD::TESTM, 0),
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X86_INTRINSIC_DATA(avx512_ptestm_b_512, CMP_MASK, X86ISD::TESTM, 0),
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@ -106,6 +106,50 @@ define <64 x i8>@test_int_x86_avx512_mask_loadu_b_512(i8* %ptr, i8* %ptr2, <64 x
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ret <64 x i8> %res2
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}
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declare <8 x i64> @llvm.x86.avx512.psll.dq.512(<8 x i64>, i32)
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define <8 x i64>@test_int_x86_avx512_mask_psll_dq_512(<8 x i64> %x0) {
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; AVX512BW-LABEL: test_int_x86_avx512_mask_psll_dq_512:
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; AVX512BW: ## BB#0:
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; AVX512BW-NEXT: vpslldq $8, %zmm0, %zmm1
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; AVX512BW-NEXT: vpslldq $4, %zmm0, %zmm0
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; AVX512BW-NEXT: vpaddq %zmm0, %zmm1, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512F-32-LABEL: test_int_x86_avx512_mask_psll_dq_512:
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; AVX512F-32: # BB#0:
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; AVX512F-32-NEXT: vpslldq $8, %zmm0, %zmm1
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; AVX512F-32-NEXT: vpslldq $4, %zmm0, %zmm0
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; AVX512F-32-NEXT: vpaddq %zmm0, %zmm1, %zmm0
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; AVX512F-32-NEXT: retl
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%res = call <8 x i64> @llvm.x86.avx512.psll.dq.512(<8 x i64> %x0, i32 8)
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%res1 = call <8 x i64> @llvm.x86.avx512.psll.dq.512(<8 x i64> %x0, i32 4)
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%res2 = add <8 x i64> %res, %res1
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ret <8 x i64> %res2
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}
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declare <8 x i64> @llvm.x86.avx512.psrl.dq.512(<8 x i64>, i32)
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define <8 x i64>@test_int_x86_avx512_mask_psrl_dq_512(<8 x i64> %x0) {
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; AVX512BW-LABEL: test_int_x86_avx512_mask_psrl_dq_512:
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; AVX512BW: ## BB#0:
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; AVX512BW-NEXT: vpsrldq $8, %zmm0, %zmm1
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; AVX512BW-NEXT: vpsrldq $4, %zmm0, %zmm0
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; AVX512BW-NEXT: vpaddq %zmm0, %zmm1, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrl_dq_512:
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; AVX512F-32: # BB#0:
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; AVX512F-32-NEXT: vpsrldq $8, %zmm0, %zmm1
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; AVX512F-32-NEXT: vpsrldq $4, %zmm0, %zmm0
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; AVX512F-32-NEXT: vpaddq %zmm0, %zmm1, %zmm0
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; AVX512F-32-NEXT: retl
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%res = call <8 x i64> @llvm.x86.avx512.psrl.dq.512(<8 x i64> %x0, i32 8)
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%res1 = call <8 x i64> @llvm.x86.avx512.psrl.dq.512(<8 x i64> %x0, i32 4)
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%res2 = add <8 x i64> %res, %res1
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ret <8 x i64> %res2
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}
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declare <64 x i8> @llvm.x86.avx512.mask.palignr.512(<64 x i8>, <64 x i8>, i32, <64 x i8>, i64)
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define <64 x i8>@test_int_x86_avx512_mask_palignr_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x3, i64 %x4) {
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@ -1,4 +1,3 @@
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; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW
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; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F-32
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@ -2604,49 +2603,6 @@ define <32 x i16>@test_int_x86_avx512_mask_dbpsadbw_512(<64 x i8> %x0, <64 x i8>
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ret <32 x i16> %res4
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}
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declare <8 x i64> @llvm.x86.avx512.psll.dq.512(<8 x i64>, i32)
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define <8 x i64>@test_int_x86_avx512_mask_psll_dq_512(<8 x i64> %x0) {
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; AVX512BW-LABEL: test_int_x86_avx512_mask_psll_dq_512:
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; AVX512BW: ## BB#0:
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; AVX512BW-NEXT: vpslldq $8, %zmm0, %zmm1
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; AVX512BW-NEXT: vpslldq $4, %zmm0, %zmm0
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; AVX512BW-NEXT: vpaddq %zmm0, %zmm1, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512F-32-LABEL: test_int_x86_avx512_mask_psll_dq_512:
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; AVX512F-32: # BB#0:
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; AVX512F-32-NEXT: vpslldq $8, %zmm0, %zmm1
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; AVX512F-32-NEXT: vpslldq $4, %zmm0, %zmm0
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; AVX512F-32-NEXT: vpaddq %zmm0, %zmm1, %zmm0
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; AVX512F-32-NEXT: retl
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%res = call <8 x i64> @llvm.x86.avx512.psll.dq.512(<8 x i64> %x0, i32 8)
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%res1 = call <8 x i64> @llvm.x86.avx512.psll.dq.512(<8 x i64> %x0, i32 4)
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%res2 = add <8 x i64> %res, %res1
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ret <8 x i64> %res2
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}
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declare <8 x i64> @llvm.x86.avx512.psrl.dq.512(<8 x i64>, i32)
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define <8 x i64>@test_int_x86_avx512_mask_psrl_dq_512(<8 x i64> %x0) {
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; AVX512BW-LABEL: test_int_x86_avx512_mask_psrl_dq_512:
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; AVX512BW: ## BB#0:
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; AVX512BW-NEXT: vpsrldq $8, %zmm0, %zmm1
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; AVX512BW-NEXT: vpsrldq $4, %zmm0, %zmm0
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; AVX512BW-NEXT: vpaddq %zmm0, %zmm1, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrl_dq_512:
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; AVX512F-32: # BB#0:
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; AVX512F-32-NEXT: vpsrldq $8, %zmm0, %zmm1
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; AVX512F-32-NEXT: vpsrldq $4, %zmm0, %zmm0
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; AVX512F-32-NEXT: vpaddq %zmm0, %zmm1, %zmm0
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; AVX512F-32-NEXT: retl
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%res = call <8 x i64> @llvm.x86.avx512.psrl.dq.512(<8 x i64> %x0, i32 8)
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%res1 = call <8 x i64> @llvm.x86.avx512.psrl.dq.512(<8 x i64> %x0, i32 4)
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%res2 = add <8 x i64> %res, %res1
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ret <8 x i64> %res2
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}
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declare <8 x i64> @llvm.x86.avx512.psad.bw.512(<64 x i8>, <64 x i8>)
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define <8 x i64>@test_int_x86_avx512_mask_psadb_w_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2){
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