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Synthetic instructions RET and RETL need to have all 3 parameters specified

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17002 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-10-14 22:32:49 +00:00
parent 45a68268a4
commit 3df04c58fc
2 changed files with 12 additions and 8 deletions
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10
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -47,10 +47,12 @@ def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move
// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in
def RET : F3_2<2, 0b111000, "ret">;
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in
def RETL: F3_2<2, 0b111000, "retl">;
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
def RET : F3_2<2, 0b111000, "ret">;
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
def RETL: F3_2<2, 0b111000, "retl">;
}
// CMP is a special case of SUBCC where destination is ignored, by setting it to
// %g0 (hardwired zero).
// FIXME: should keep track of the fact that it defs the integer condition codes

10
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -47,10 +47,12 @@ def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move
// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in
def RET : F3_2<2, 0b111000, "ret">;
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in
def RETL: F3_2<2, 0b111000, "retl">;
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
def RET : F3_2<2, 0b111000, "ret">;
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
def RETL: F3_2<2, 0b111000, "retl">;
}
// CMP is a special case of SUBCC where destination is ignored, by setting it to
// %g0 (hardwired zero).
// FIXME: should keep track of the fact that it defs the integer condition codes