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fsel generation for f32 and f64 select
generate compare immediate for integer compare with constant fold setcc into branch fold setcc into select Code generation quality for Shootout is now on par with the Simple ISel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20968 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
5e99dd9c2b
commit
3e89716ad7
@ -54,6 +54,9 @@ namespace {
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setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
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addLegalFPImmediate(+0.0); // Necessary for FSEL
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addLegalFPImmediate(-0.0); //
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computeRegisterProperties();
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}
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@ -478,7 +481,7 @@ public:
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/// placed in Imm.
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///
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static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
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unsigned& Imm) {
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unsigned& Imm, bool U = false) {
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if (N.getOpcode() != ISD::Constant) return 0;
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int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
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@ -498,9 +501,33 @@ static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
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case ISD::MUL:
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if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
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break;
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case ISD::SETCC:
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if (U && (v >= 0 && v <= 65535)) { Imm = v & 0xFFFF; return 1; }
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if (!U && (v <= 32767 && v >= -32768)) { Imm = v & 0xFFFF; return 1; }
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break;
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}
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return 0;
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}
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/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
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/// to Condition. If the Condition is unordered or unsigned, the bool argument
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/// U is set to true, otherwise it is set to false.
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static unsigned getBCCForSetCC(unsigned Condition, bool& U) {
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U = false;
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switch (Condition) {
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default: assert(0 && "Unknown condition!"); abort();
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case ISD::SETEQ: return PPC::BEQ;
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case ISD::SETNE: return PPC::BNE;
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case ISD::SETULT: U = true;
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case ISD::SETLT: return PPC::BLT;
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case ISD::SETULE: U = true;
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case ISD::SETLE: return PPC::BLE;
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case ISD::SETUGT: U = true;
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case ISD::SETGT: return PPC::BGT;
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case ISD::SETUGE: U = true;
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case ISD::SETGE: return PPC::BGE;
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}
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}
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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@ -539,15 +566,39 @@ void ISel::SelectBranchCC(SDOperand N)
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assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
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unsigned Opc;
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unsigned Opc, Tmp1, Tmp2;
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Select(N.getOperand(0)); //chain
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SDOperand CC = N.getOperand(1);
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//Give up and do the stupid thing
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unsigned Tmp1 = SelectExpr(CC);
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(0);
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BuildMI(BB, PPC::BNE, 2).addReg(PPC::CR0).addMBB(Dest);
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// If the first operand to the select is a SETCC node, then we can fold it
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// into the branch that selects which value to return.
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SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(1).Val);
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if (SetCC && N.getOperand(1).getOpcode() == ISD::SETCC &&
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MVT::isInteger(SetCC->getOperand(0).getValueType())) {
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bool U;
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Opc = getBCCForSetCC(SetCC->getCondition(), U);
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Tmp1 = SelectExpr(SetCC->getOperand(0));
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// Pass the optional argument U to canUseAsImmediateForOpcode for SETCC,
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// so that it knows whether the SETCC immediate range is signed or not.
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if (1 == canUseAsImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
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Tmp2, U)) {
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if (U)
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
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else
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BuildMI(BB, PPC::CMPWI, 2, PPC::CR0).addReg(Tmp1).addSImm(Tmp2);
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} else {
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Tmp2 = SelectExpr(SetCC->getOperand(1));
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BuildMI(BB, U ? PPC::CMPLW : PPC::CMPW, 2, PPC::CR0).addReg(Tmp1)
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.addReg(Tmp2);
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}
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} else {
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(0);
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Opc = PPC::BNE;
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}
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BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(Dest);
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return;
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}
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@ -565,10 +616,77 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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assert(0 && "Node not handled!\n");
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case ISD::SELECT: {
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Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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// FIXME: generate FSEL here
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// Attempt to generate FSEL. We can do this whenever we have an FP result,
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// and an FP comparison in the SetCC node.
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SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
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if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
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!MVT::isInteger(SetCC->getOperand(0).getValueType()) &&
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SetCC->getCondition() != ISD::SETEQ &&
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SetCC->getCondition() != ISD::SETNE) {
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MVT::ValueType VT = SetCC->getOperand(0).getValueType();
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Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
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unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
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unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
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if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
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switch(SetCC->getCondition()) {
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default: assert(0 && "Invalid FSEL condition"); abort();
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case ISD::SETULT:
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case ISD::SETLT:
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(FV).addReg(TV);
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return Result;
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case ISD::SETUGE:
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case ISD::SETGE:
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
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return Result;
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case ISD::SETUGT:
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case ISD::SETGT: {
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Tmp2 = MakeReg(VT);
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BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(FV).addReg(TV);
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return Result;
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}
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case ISD::SETULE:
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case ISD::SETLE: {
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Tmp2 = MakeReg(VT);
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BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
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return Result;
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}
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}
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} else {
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Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
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Tmp2 = SelectExpr(SetCC->getOperand(1));
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Tmp3 = MakeReg(VT);
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switch(SetCC->getCondition()) {
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default: assert(0 && "Invalid FSEL condition"); abort();
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case ISD::SETULT:
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case ISD::SETLT:
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
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return Result;
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case ISD::SETUGE:
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case ISD::SETGE:
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
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return Result;
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case ISD::SETUGT:
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case ISD::SETGT:
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
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return Result;
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case ISD::SETULE:
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case ISD::SETLE:
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
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return Result;
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}
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}
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assert(0 && "Should never get here");
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return 0;
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}
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// Create an iterator with which to insert the MBB for copying the false
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// value and the MBB to hold the PHI instruction for this SetCC.
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MachineBasicBlock *thisMBB = BB;
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@ -582,6 +700,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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// cmpTY cr0, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(0);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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@ -1085,24 +1204,29 @@ unsigned ISel::SelectExpr(SDOperand N) {
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bool U = false;
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bool IsInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
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switch (SetCC->getCondition()) {
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default: Node->dump(); assert(0 && "Unknown comparison!");
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case ISD::SETEQ: Opc = PPC::BEQ; break;
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case ISD::SETNE: Opc = PPC::BNE; break;
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case ISD::SETULT: U = true;
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case ISD::SETLT: Opc = PPC::BLT; break;
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case ISD::SETULE: U = true;
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case ISD::SETLE: Opc = PPC::BLE; break;
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case ISD::SETUGT: U = true;
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case ISD::SETGT: Opc = PPC::BGT; break;
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case ISD::SETUGE: U = true;
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case ISD::SETGE: Opc = PPC::BGE; break;
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}
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// FIXME: Is there a situation in which we would ever need to emit fcmpo?
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static const unsigned CompareOpcodes[] =
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{ PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
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unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
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// Set the branch opcode to use below
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Opc = getBCCForSetCC(SetCC->getCondition(), U);
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// Try and use an integer compare with immediate, if applicable.
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// Normal setcc uses the sign-extended immediate range, unsigned setcc
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// uses the zero extended immediate range.
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if (IsInteger &&
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1 == canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2, U)) {
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Tmp1 = SelectExpr(N.getOperand(0));
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if (U)
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
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else
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BuildMI(BB, PPC::CMPWI, 2, PPC::CR0).addReg(Tmp1).addSImm(Tmp2);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
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BuildMI(BB, CompareOpc, 2, PPC::CR0).addReg(Tmp1).addReg(Tmp2);
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}
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// Create an iterator with which to insert the MBB for copying the false
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// value and the MBB to hold the PHI instruction for this SetCC.
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@ -1116,9 +1240,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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// cmpTY cr0, r1, r2
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// %TrueValue = li 1
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// bCC sinkMBB
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, CompareOpc, 2, PPC::CR0).addReg(Tmp1).addReg(Tmp2);
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unsigned TrueValue = MakeReg(MVT::i32);
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BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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@ -1152,8 +1273,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return 0;
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case ISD::SELECT: {
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Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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// Create an iterator with which to insert the MBB for copying the false
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// value and the MBB to hold the PHI instruction for this SetCC.
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MachineBasicBlock *thisMBB = BB;
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@ -1161,17 +1280,44 @@ unsigned ISel::SelectExpr(SDOperand N) {
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// If the first operand to the select is a SETCC node, then we can fold it
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// into the branch that selects which value to return.
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SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
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if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
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MVT::isInteger(SetCC->getOperand(0).getValueType())) {
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bool U;
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Opc = getBCCForSetCC(SetCC->getCondition(), U);
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Tmp1 = SelectExpr(SetCC->getOperand(0));
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// Pass the optional argument U to canUseAsImmediateForOpcode for SETCC,
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// so that it knows whether the SETCC immediate range is signed or not.
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if (1 == canUseAsImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
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Tmp2, U)) {
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if (U)
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
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else
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BuildMI(BB, PPC::CMPWI, 2, PPC::CR0).addReg(Tmp1).addSImm(Tmp2);
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} else {
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Tmp2 = SelectExpr(SetCC->getOperand(1));
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BuildMI(BB, U ? PPC::CMPLW : PPC::CMPW, 2, PPC::CR0).addReg(Tmp1)
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.addReg(Tmp2);
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}
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} else {
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Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(0);
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Opc = PPC::BNE;
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}
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY cr0, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(0);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
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BuildMI(BB, PPC::BNE, 2).addReg(PPC::CR0).addMBB(sinkMBB);
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BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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