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[GlobalISel] Add a test for the tablegen selector emitter backend.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294075 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2017-02-04 00:47:05 +00:00
parent 40d6dfa91e
commit 3ebe403844
1 changed files with 56 additions and 0 deletions
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test/TableGen/GlobalISelEmitter.td Normal file
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// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
//===- Define the necessary boilerplate for our test target. --------------===//
def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; }
def R0 : Register<"r0">;
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
class I<dag OOps, dag IOps, list<dag> Pat>
: Instruction {
let Namespace = "MyTarget";
let OutOperandList = OOps;
let InOperandList = IOps;
let Pattern = Pat;
}
//===- Test the function definition boilerplate. --------------------------===//
// CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I) const {
// CHECK: const MachineRegisterInfo &MRI = I.getParent()->getParent()->getRegInfo();
//===- Test a simple pattern with regclass operands. ----------------------===//
// CHECK: if ((I.getOpcode() == TargetOpcode::G_ADD) &&
// CHECK-NEXT: (((MRI.getType(I.getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: (((MRI.getType(I.getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: (((MRI.getType(I.getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(2).getReg(), MRI, TRI)))))) {
// CHECK-NEXT: I.setDesc(TII.get(MyTarget::ADD));
// CHECK-NEXT: constrainSelectedInstRegOperands(I, TII, TRI, RBI);
// CHECK-NEXT: return true;
// CHECK-NEXT: }
def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
[(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
//===- Test a pattern with an MBB operand. --------------------------------===//
// CHECK: if ((I.getOpcode() == TargetOpcode::G_BR) &&
// CHECK-NEXT: (((I.getOperand(0).isMBB())))) {
// CHECK-NEXT: I.setDesc(TII.get(MyTarget::BR));
// CHECK-NEXT: constrainSelectedInstRegOperands(I, TII, TRI, RBI);
// CHECK-NEXT: return true;
// CHECK-NEXT: }
def BR : I<(outs), (ins unknown:$target),
[(br bb:$target)]>;