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Fix MSP430 calling convention to match MSPGCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192678 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -23,18 +23,15 @@ def RetCC_MSP430 : CallingConv<[
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//===----------------------------------------------------------------------===//
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// MSP430 Argument Calling Conventions
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//===----------------------------------------------------------------------===//
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def CC_MSP430 : CallingConv<[
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def CC_MSP430_AssignStack : CallingConv<[
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// Pass by value if the byval attribute is given
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CCIfByVal<CCPassByVal<2, 2>>,
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// Promote i8 arguments to i16.
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CCIfType<[i8], CCPromoteToType<i16>>,
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// The first 4 integer arguments of non-varargs functions are passed in
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// integer registers.
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CCIfNotVarArg<CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>>>,
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// Integer values get stored in stack slots that are 2 bytes in
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// size and 2-byte aligned.
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CCIfType<[i16], CCAssignToStack<2, 2>>
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]>;
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@ -250,6 +250,123 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
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#include "MSP430GenCallingConv.inc"
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/// For each argument in a function store the number of pieces it is composed
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/// of.
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template<typename ArgT>
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static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
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SmallVectorImpl<unsigned> &Out) {
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unsigned CurrentArgIndex = ~0U;
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for (unsigned i = 0, e = Args.size(); i != e; i++) {
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if (CurrentArgIndex == Args[i].OrigArgIndex) {
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Out.back()++;
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} else {
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Out.push_back(1);
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CurrentArgIndex++;
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}
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}
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}
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static void AnalyzeVarArgs(CCState &State,
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const SmallVectorImpl<ISD::OutputArg> &Outs) {
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State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
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}
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static void AnalyzeVarArgs(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) {
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State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
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}
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/// Analyze incoming and outgoing function arguments. We need custom C++ code
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/// to handle special constraints in the ABI like reversing the order of the
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/// pieces of splitted arguments. In addition, all pieces of a certain argument
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/// have to be passed either using registers or the stack but never mixing both.
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template<typename ArgT>
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static void AnalyzeArguments(CCState &State,
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SmallVectorImpl<CCValAssign> &ArgLocs,
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const SmallVectorImpl<ArgT> &Args) {
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static const uint16_t RegList[] = {
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MSP430::R15W, MSP430::R14W, MSP430::R13W, MSP430::R12W
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};
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static const unsigned NbRegs = array_lengthof(RegList);
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if (State.isVarArg()) {
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AnalyzeVarArgs(State, Args);
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return;
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}
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SmallVector<unsigned, 4> ArgsParts;
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ParseFunctionArgs(Args, ArgsParts);
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unsigned RegsLeft = NbRegs;
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bool UseStack = false;
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unsigned ValNo = 0;
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for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
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MVT ArgVT = Args[ValNo].VT;
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ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
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MVT LocVT = ArgVT;
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CCValAssign::LocInfo LocInfo = CCValAssign::Full;
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// Promote i8 to i16
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if (LocVT == MVT::i8) {
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LocVT = MVT::i16;
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if (ArgFlags.isSExt())
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LocInfo = CCValAssign::SExt;
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else if (ArgFlags.isZExt())
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LocInfo = CCValAssign::ZExt;
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else
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LocInfo = CCValAssign::AExt;
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}
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// Handle byval arguments
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if (ArgFlags.isByVal()) {
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State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
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continue;
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}
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unsigned Parts = ArgsParts[i];
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if (!UseStack && Parts <= RegsLeft) {
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unsigned FirstVal = ValNo;
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for (unsigned j = 0; j < Parts; j++) {
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unsigned Reg = State.AllocateReg(RegList, NbRegs);
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State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
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RegsLeft--;
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}
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// Reverse the order of the pieces to agree with the "big endian" format
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// required in the calling convention ABI.
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SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
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std::reverse(B, B + Parts);
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} else {
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UseStack = true;
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for (unsigned j = 0; j < Parts; j++)
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CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
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}
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}
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}
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static void AnalyzeRetResult(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) {
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State.AnalyzeCallResult(Ins, RetCC_MSP430);
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}
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static void AnalyzeRetResult(CCState &State,
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const SmallVectorImpl<ISD::OutputArg> &Outs) {
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State.AnalyzeReturn(Outs, RetCC_MSP430);
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}
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template<typename ArgT>
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static void AnalyzeReturnValues(CCState &State,
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SmallVectorImpl<CCValAssign> &RVLocs,
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const SmallVectorImpl<ArgT> &Args) {
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AnalyzeRetResult(State, Args);
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// Reverse splitted return values to get the "big endian" format required
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// to agree with the calling convention ABI.
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std::reverse(RVLocs.begin(), RVLocs.end());
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}
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SDValue
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MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv,
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@ -325,7 +442,7 @@ MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
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AnalyzeArguments(CCInfo, ArgLocs, Ins);
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// Create frame index for the start of the first vararg value
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if (isVarArg) {
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@ -423,7 +540,7 @@ MSP430TargetLowering::LowerReturn(SDValue Chain,
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getTargetMachine(), RVLocs, *DAG.getContext());
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// Analize return values.
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CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
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AnalyzeReturnValues(CCInfo, RVLocs, Outs);
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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@ -471,8 +588,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
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AnalyzeArguments(CCInfo, ArgLocs, Outs);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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@ -610,7 +726,7 @@ MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
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AnalyzeReturnValues(CCInfo, RVLocs, Ins);
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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118
test/CodeGen/MSP430/cc_args.ll
Normal file
118
test/CodeGen/MSP430/cc_args.ll
Normal file
@ -0,0 +1,118 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
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target triple = "msp430---elf"
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define void @test() #0 {
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entry:
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; CHECK: test:
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; CHECK: mov.w #1, r15
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; CHECK: call #f_i16
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call void @f_i16(i16 1)
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; CHECK: mov.w #772, r14
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; CHECK: mov.w #258, r15
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; CHECK: call #f_i32
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call void @f_i32(i32 16909060)
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; CHECK: mov.w #1800, r12
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; CHECK: mov.w #1286, r13
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; CHECK: mov.w #772, r14
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; CHECK: mov.w #258, r15
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; CHECK: call #f_i64
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call void @f_i64(i64 72623859790382856)
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; CHECK: mov.w #772, r14
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; CHECK: mov.w #258, r15
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; CHECK: mov.w #1800, r12
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; CHECK: mov.w #1286, r13
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; CHECK: call #f_i32_i32
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call void @f_i32_i32(i32 16909060, i32 84281096)
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; CHECK: mov.w #1, r15
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; CHECK: mov.w #772, r13
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; CHECK: mov.w #258, r14
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; CHECK: mov.w #2, r12
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; CHECK: call #f_i16_i32_i16
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call void @f_i16_i32_i16(i16 1, i32 16909060, i16 2)
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; CHECK: mov.w #2, 8(r1)
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; CHECK: mov.w #258, 6(r1)
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; CHECK: mov.w #772, 4(r1)
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; CHECK: mov.w #1286, 2(r1)
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; CHECK: mov.w #1800, 0(r1)
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; CHECK: mov.w #1, r15
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; CHECK: call #f_i16_i64_i16
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call void @f_i16_i64_i16(i16 1, i64 72623859790382856, i16 2)
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ret void
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}
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@g_i16 = common global i16 0, align 2
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@g_i32 = common global i32 0, align 2
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@g_i64 = common global i64 0, align 2
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define void @f_i16(i16 %a) #0 {
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; CHECK: f_i16:
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; CHECK: mov.w r15, &g_i16
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store volatile i16 %a, i16* @g_i16, align 2
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ret void
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}
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define void @f_i32(i32 %a) #0 {
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; CHECK: f_i32:
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; CHECK: mov.w r15, &g_i32+2
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; CHECK: mov.w r14, &g_i32
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store volatile i32 %a, i32* @g_i32, align 2
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ret void
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}
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define void @f_i64(i64 %a) #0 {
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; CHECK: f_i64:
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; CHECK: mov.w r15, &g_i64+6
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; CHECK: mov.w r14, &g_i64+4
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; CHECK: mov.w r13, &g_i64+2
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; CHECK: mov.w r12, &g_i64
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store volatile i64 %a, i64* @g_i64, align 2
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ret void
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}
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define void @f_i32_i32(i32 %a, i32 %b) #0 {
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; CHECK: f_i32_i32:
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; CHECK: mov.w r15, &g_i32+2
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; CHECK: mov.w r14, &g_i32
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store volatile i32 %a, i32* @g_i32, align 2
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; CHECK: mov.w r13, &g_i32+2
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; CHECK: mov.w r12, &g_i32
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store volatile i32 %b, i32* @g_i32, align 2
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ret void
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}
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define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
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; CHECK: f_i16_i32_i16:
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; CHECK: mov.w r15, &g_i16
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store volatile i16 %a, i16* @g_i16, align 2
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; CHECK: mov.w r14, &g_i32+2
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; CHECK: mov.w r13, &g_i32
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store volatile i32 %b, i32* @g_i32, align 2
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; CHECK: mov.w r12, &g_i16
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store volatile i16 %c, i16* @g_i16, align 2
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ret void
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}
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define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
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; CHECK: f_i16_i64_i16:
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; CHECK: mov.w r15, &g_i16
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store volatile i16 %a, i16* @g_i16, align 2
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;CHECK: mov.w 10(r4), &g_i64+6
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;CHECK: mov.w 8(r4), &g_i64+4
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;CHECK: mov.w 6(r4), &g_i64+2
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;CHECK: mov.w 4(r4), &g_i64
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store volatile i64 %b, i64* @g_i64, align 2
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;CHECK: mov.w 12(r4), &g_i16
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store volatile i16 %c, i16* @g_i16, align 2
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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61
test/CodeGen/MSP430/cc_ret.ll
Normal file
61
test/CodeGen/MSP430/cc_ret.ll
Normal file
@ -0,0 +1,61 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
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target triple = "msp430---elf"
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define void @test() #0 {
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entry:
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; CHECK: test:
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; CHECK: call #f_i16
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; CHECK: mov.w r15, &g_i16
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%0 = call i16 @f_i16()
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store volatile i16 %0, i16* @g_i16
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; CHECK: call #f_i32
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; CHECK: mov.w r15, &g_i32+2
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; CHECK: mov.w r14, &g_i32
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%1 = call i32 @f_i32()
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store volatile i32 %1, i32* @g_i32
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; CHECK: call #f_i64
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; CHECK: mov.w r15, &g_i64+6
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; CHECK: mov.w r14, &g_i64+4
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; CHECK: mov.w r13, &g_i64+2
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; CHECK: mov.w r12, &g_i64
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%2 = call i64 @f_i64()
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store volatile i64 %2, i64* @g_i64
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ret void
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}
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@g_i16 = common global i16 0, align 2
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@g_i32 = common global i32 0, align 2
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@g_i64 = common global i64 0, align 2
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define i16 @f_i16() #0 {
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; CHECK: f_i16:
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; CHECK: mov.w #1, r15
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; CHECK: ret
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ret i16 1
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}
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define i32 @f_i32() #0 {
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; CHECK: f_i32:
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; CHECK: mov.w #772, r14
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; CHECK: mov.w #258, r15
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; CHECK: ret
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ret i32 16909060
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}
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define i64 @f_i64() #0 {
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; CHECK: f_i64:
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; CHECK: mov.w #1800, r12
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; CHECK: mov.w #1286, r13
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; CHECK: mov.w #772, r14
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; CHECK: mov.w #258, r15
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; CHECK: ret
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ret i64 72623859790382856
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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