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[FastISel][AArch64] Use the proper FMOV instruction to materialize a +0.0.

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Use FMOVWSr/FMOVXDr instead of FMOVSr/FMOVDr, which have the proper register
class to be used with the zero register. This makes the MachineInstruction
verifier happy again.

This is related to <rdar://problem/18027157>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216040 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-08-20 01:10:36 +00:00
parent e0134d95cc
commit 3ef392c4e2
2 changed files with 2 additions and 2 deletions
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2
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -291,7 +291,7 @@ unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
// register, because the immediate version of fmov cannot encode zero.
if (Val.isPosZero()) {
unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
unsigned Opc = Is64Bit ? AArch64::FMOVDr : AArch64::FMOVSr;
unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
.addReg(ZReg, getKillRegState(true));
return ResultReg;

2
test/CodeGen/AArch64/arm64-fast-isel-materialize.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; Materialize using fmov
define float @fmov_float1() {