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[ARM] When generating a vpaddl node the input lane type is not always the type of the

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add operation since extract_vector_elt can perform an extend operation. Get the input lane
type from the vector on which we're performing the vpaddl operation on and extend or
truncate it to the output type of the original add node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205523 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2014-04-03 10:44:27 +00:00
parent 10914379f6
commit 3f11cd0d25
2 changed files with 16 additions and 2 deletions
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7
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -8254,7 +8254,9 @@ static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
// Get widened type and narrowed type.
MVT widenType;
unsigned numElem = VT.getVectorNumElements();
switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
EVT inputLaneType = Vec.getValueType().getVectorElementType();
switch (inputLaneType.getSimpleVT().SimpleTy) {
case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
@ -8264,7 +8266,8 @@ static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
widenType, &Ops[0], Ops.size());
return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, tmp);
unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
}
static SDValue findMUL_LOHI(SDValue V) {

11
test/CodeGen/ARM/vpadd.ll
View File

@ -152,6 +152,17 @@ define void @addCombineToVPADDL() nounwind ssp {
ret void
}
; Legalization produces a EXTRACT_VECTOR_ELT DAG node which performs an extend from
; i16 to i32. In this case the input for the formed VPADDL needs to be a vector of i16s.
define <2 x i16> @fromExtendingExtractVectorElt(<4 x i16> %in) {
;CHECK-LABEL: fromExtendingExtractVectorElt:
;CHECK: vpaddl.s16
%tmp1 = shufflevector <4 x i16> %in, <4 x i16> undef, <2 x i32> <i32 0, i32 2>
%tmp2 = shufflevector <4 x i16> %in, <4 x i16> undef, <2 x i32> <i32 1, i32 3>
%x = add <2 x i16> %tmp2, %tmp1
ret <2 x i16> %x
}
declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone