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reorganize logic; NFCI (retry r251349)

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This is a preliminary step before adding another optimization
to PerformBITCASTCombine().

..and I really hope it's NFC this time!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251357 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2015-10-26 21:54:14 +00:00
parent 830544779e
commit 3fdc848a44
1 changed files with 13 additions and 13 deletions
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26
lib/Target/X86/X86ISelLowering.cpp
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@ -23123,21 +23123,21 @@ static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
EltNo);
}
/// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
/// special and don't usually play with other vector types, it's better to
/// handle them early to be sure we emit efficient code by avoiding
/// store-load conversions.
static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
if (N->getValueType(0) != MVT::x86mmx ||
N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
N->getOperand(0)->getValueType(0) != MVT::v2i32)
return SDValue();
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
SDValue V = N->getOperand(0);
ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
N->getValueType(0), V.getOperand(0));
// Detect bitcasts between i32 to x86mmx low word. Since MMX types are
// special and don't usually play with other vector types, it's better to
// handle them early to be sure we emit efficient code by avoiding
// store-load conversions.
if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
N0.getValueType() == MVT::v2i32 &&
isa<ConstantSDNode>(N0.getOperand(1))) {
SDValue N00 = N0->getOperand(0);
if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
}
return SDValue();
}