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All store instructions really want 'rd' in the first field.
Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and expect %fsr as the parameter in assembly. They are disabled (since not used) until an encoding, both for code generation and output, is chosen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6619 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -678,7 +678,8 @@ def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
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// Section A.51: Store Barrier - p224
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// Not currently used in the Sparc backend
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// Section A.52: Store Floating-point -p225
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// Section A.52: Store Floating-point - p225
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// Store instructions all want their rd register first
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def STFr : F3_1rd<3, 0b100100, "st">; // st r, [r+r]
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def STFi : F3_2rd<3, 0b100100, "st">; // st r, [r+i]
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def STDFr : F3_1rd<3, 0b100111, "std">; // std r, [r+r]
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@ -690,25 +691,31 @@ def STQFr : F3_1rd<3, 0b100110, "stq">; // stq r, [r+r]
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def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i]
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#endif
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// FIXME: An encoding needs to be chosen here, because STFSRx expect rd=0,
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// while STXFSRx expect rd=1, but assembly syntax dictates %fsr as first arg.
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// These are being disabled because they aren't used in the Sparc backend.
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#if 0
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set isDeprecated = 1 in {
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def STFSRr : F3_1<3, 0b100101, "st">; // st r, [r+r]
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def STFSRi : F3_2<3, 0b100101, "st">; // st r, [r+i]
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def STFSRr : F3_1<3, 0b100101, "st">; // st %fsr, [r+r]
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def STFSRi : F3_2<3, 0b100101, "st">; // st %fsr, [r+i]
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}
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def STXFSRr : F3_1<3, 0b100101, "stq">; // stx r, [r+r]
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def STXFSRi : F3_2<3, 0b100101, "stq">; // stx r, [r+i]
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def STXFSRr : F3_1<3, 0b100101, "stx">; // stx %fsr, [r+r]
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def STXFSRi : F3_2<3, 0b100101, "stx">; // stx %fsr, [r+i]
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#endif
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// Section A.53: Store Floating-Point into Alternate Space - p227
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// Not currently used in the Sparc backend
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// Section A.54: Store Integer - p229
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def STBr : F3_1<3, 0b000101, "stb">; // stb r, [r+r]
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def STBi : F3_2<3, 0b000101, "stb">; // stb r, [r+i]
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def STHr : F3_1<3, 0b000110, "stb">; // stb r, [r+r]
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def STHi : F3_2<3, 0b000110, "stb">; // stb r, [r+i]
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def STWr : F3_1<3, 0b000100, "stb">; // stb r, [r+r]
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def STWi : F3_2<3, 0b000100, "stb">; // stb r, [r+i]
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def STXr : F3_1<3, 0b001110, "stb">; // stb r, [r+r]
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def STXi : F3_2<3, 0b001110, "stb">; // stb r, [r+i]
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// Store instructions all want their rd register first
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def STBr : F3_1rd<3, 0b000101, "stb">; // stb r, [r+r]
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def STBi : F3_2rd<3, 0b000101, "stb">; // stb r, [r+i]
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def STHr : F3_1rd<3, 0b000110, "sth">; // stb r, [r+r]
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def STHi : F3_2rd<3, 0b000110, "sth">; // stb r, [r+i]
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def STWr : F3_1rd<3, 0b000100, "stw">; // stb r, [r+r]
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def STWi : F3_2rd<3, 0b000100, "stw">; // stb r, [r+i]
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def STXr : F3_1rd<3, 0b001110, "stx">; // stb r, [r+r]
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def STXi : F3_2rd<3, 0b001110, "stx">; // stb r, [r+i]
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// Section A.55: Store Integer into Alternate Space - p231
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// Not currently used in the Sparc backend
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