From 4072886a690a853c57c79a87a6423a7bfe0ce61f Mon Sep 17 00:00:00 2001 From: Daniel Dunbar Date: Thu, 20 May 2010 20:20:32 +0000 Subject: [PATCH] tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/Target.td | 3 +++ utils/TableGen/X86RecognizableInstr.cpp | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index cc19e0de8eb..ee9e83f5d1c 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -221,6 +221,9 @@ class Instruction { // purposes. bit isCodeGenOnly = 0; + // Is this instruction a pseudo instruction for use by the assembler parser. + bit isAsmParserOnly = 0; + InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. string Constraints = ""; // OperandConstraint, e.g. $src = $dst. diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 94ed15b0c37..b7085ae6c7b 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -230,6 +230,10 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables, const CodeGenInstruction &insn, InstrUID uid) { + // Ignore "asm parser only" instructions. + if (insn.TheDef->getValueAsBit("isAsmParserOnly")) + return; + RecognizableInstr recogInstr(tables, insn, uid); recogInstr.emitInstructionSpecifier(tables);