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foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33958 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -185,6 +185,19 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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abort();
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}
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/// isLowRegister - Returns true if the register is low register r0-r7.
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///
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static bool isLowRegister(unsigned Reg) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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return true;
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default:
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return false;
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}
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}
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MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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unsigned OpNum, int FI) const {
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unsigned Opc = MI->getOpcode();
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@ -206,10 +219,16 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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case ARM::tMOVrr: {
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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if (!isLowRegister(SrcReg))
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// tSTRspi cannot take a high register operand.
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break;
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NewMI = BuildMI(TII.get(ARM::tSTRspi)).addReg(SrcReg).addFrameIndex(FI)
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.addImm(0);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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if (!isLowRegister(DstReg))
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// tLDRspi cannot target a high register operand.
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break;
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NewMI = BuildMI(TII.get(ARM::tLDRspi), DstReg).addFrameIndex(FI)
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.addImm(0);
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}
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@ -316,19 +335,6 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
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}
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}
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/// isLowRegister - Returns true if the register is low register r0-r7.
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///
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static bool isLowRegister(unsigned Reg) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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return true;
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default:
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return false;
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}
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}
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/// calcNumMI - Returns the number of instructions required to materialize
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/// the specific add / sub r, c instruction.
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static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
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