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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170997 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
parent
677689cf5d
commit
40b04a481d
@ -1239,7 +1239,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
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// Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
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// handle type legalization for these operations here.
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//
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@ -1314,13 +1313,11 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setPrefFunctionAlignment(4); // 2^4 bytes.
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}
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EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
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if (!VT.isVector()) return MVT::i8;
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return VT.changeVectorElementTypeToInteger();
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}
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/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
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/// the desired ByVal argument alignment.
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static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
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@ -1525,7 +1522,6 @@ bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Return Value Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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@ -1773,7 +1769,6 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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return Chain;
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}
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//===----------------------------------------------------------------------===//
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// C & StdCall & Fast Calling Convention implementation
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//===----------------------------------------------------------------------===//
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@ -2664,7 +2659,6 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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Ins, dl, DAG, InVals);
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}
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//===----------------------------------------------------------------------===//
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// Fast Calling Convention (tail call) implementation
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//===----------------------------------------------------------------------===//
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@ -2973,7 +2967,6 @@ X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
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return X86::createFastISel(funcInfo, libInfo);
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}
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//===----------------------------------------------------------------------===//
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// Other Lowering Hooks
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//===----------------------------------------------------------------------===//
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@ -3084,7 +3077,6 @@ SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
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return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
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}
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bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
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bool hasSymbolicDisplacement) {
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// Offset should fit into 32 bit immediate field.
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@ -6997,7 +6989,6 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
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getShuffleCLImmediate(SVOp), DAG);
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//===--------------------------------------------------------------------===//
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// Since no target specific shuffle was selected for this generic one,
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// lower it into other known shuffles. FIXME: this isn't true yet, but
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@ -7099,7 +7090,6 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
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return SDValue();
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}
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SDValue
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X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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SelectionDAG &DAG) const {
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@ -7464,7 +7454,6 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
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// With PIC, the address is actually $g + Offset.
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if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
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!Subtarget->is64Bit()) {
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@ -7851,7 +7840,6 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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llvm_unreachable("TLS not implemented for this target.");
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}
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/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
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/// and take a 2 x i32 value to shift plus a shift amount.
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SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
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@ -9076,7 +9064,6 @@ static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
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DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
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}
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SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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SDValue Cond;
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SDValue Op0 = Op.getOperand(0);
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@ -9729,7 +9716,6 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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Chain, Dest, CC, Cond);
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}
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// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
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// Calls to _alloca is needed to probe the stack when allocating more than 4k
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// bytes in one go. Touching the stack at 4K increments is necessary to ensure
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@ -10866,7 +10852,6 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
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int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
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SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOStore, 2, 2);
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@ -10899,7 +10884,6 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
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DAG.getConstant(1, MVT::i16)),
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DAG.getConstant(3, MVT::i16));
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return DAG.getNode((VT.getSizeInBits() < 16 ?
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ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
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}
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@ -11452,7 +11436,6 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
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}
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}
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static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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@ -11537,7 +11520,6 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
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return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
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}
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static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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EVT T = Op.getValueType();
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@ -12190,7 +12172,6 @@ bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
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return true;
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}
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bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
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if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
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return false;
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@ -14388,7 +14369,6 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
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}
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/// PerformTruncateCombine - Converts truncate operation to
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/// a sequence of vector shuffle operations.
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/// It is possible when we truncate 256-bit vector to 128-bit vector
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@ -15118,7 +15098,6 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
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return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
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// If we know that this node is legal then we know that it is going to be
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// matched by one of the SSE/AVX BLEND instructions. These instructions only
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// depend on the highest bit in each word. Try to use SimplifyDemandedBits
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@ -15416,7 +15395,6 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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/// PerformMulCombine - Optimize a single multiply with constant into two
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/// in order to implement it with two cheaper instructions, e.g.
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/// LEA + SHL, LEA + LEA.
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@ -15505,7 +15483,6 @@ static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
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}
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}
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// Hardware support for vector shifts is sparse which makes us scalarize the
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// vector operations in many cases. Also, on sandybridge ADD is faster than
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// shl.
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@ -15649,7 +15626,6 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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}
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}
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// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
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// where both setccs reference the same FP CMP, and rewrite for CMPEQSS
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// and friends. Likewise for OR -> CMPNEQSS.
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@ -16334,7 +16310,6 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
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Chains.size());
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}
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// Turn load->store of MMX types into GPR load/stores. This avoids clobbering
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// the FP state in cases where an emms may be missing.
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// A preferable solution to the general problem is to figure out the right
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@ -16640,7 +16615,6 @@ static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
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N->getOperand(0), N->getOperand(1));
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}
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/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
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static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
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// FAND(0.0, x) -> 0.0
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@ -17378,8 +17352,6 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
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return false;
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}
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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X86TargetLowering::ConstraintType
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