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Expand arith on machines without carry flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57243 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6431,7 +6431,6 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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break;
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break;
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}
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}
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}
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}
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// Expand the subcomponents.
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// Expand the subcomponents.
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SDValue LHSL, LHSH, RHSL, RHSH;
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SDValue LHSL, LHSH, RHSL, RHSH;
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ExpandOp(Node->getOperand(0), LHSL, LHSH);
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ExpandOp(Node->getOperand(0), LHSL, LHSH);
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@ -6442,6 +6441,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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LoOps[1] = RHSL;
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LoOps[1] = RHSL;
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HiOps[0] = LHSH;
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HiOps[0] = LHSH;
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HiOps[1] = RHSH;
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HiOps[1] = RHSH;
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if(TLI.isOperationLegal(ISD::ADDC, NVT)) {
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if (Node->getOpcode() == ISD::ADD) {
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if (Node->getOpcode() == ISD::ADD) {
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Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
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Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
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HiOps[2] = Lo.getValue(1);
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HiOps[2] = Lo.getValue(1);
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@ -6452,6 +6452,30 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
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Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
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}
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}
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break;
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break;
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} else {
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if (Node->getOpcode() == ISD::ADD) {
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Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
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Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
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SDValue Cmp1 = DAG.getSetCC(NVT, Lo, LoOps[0], ISD::SETULT);
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SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
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DAG.getConstant(1, NVT),
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DAG.getConstant(0, NVT));
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SDValue Cmp2 = DAG.getSetCC(NVT, Lo, LoOps[1], ISD::SETULT);
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SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
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DAG.getConstant(1, NVT),
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Carry1);
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Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
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} else {
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Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
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Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
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SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
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SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
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DAG.getConstant(1, NVT),
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DAG.getConstant(0, NVT));
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Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
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}
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break;
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}
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}
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}
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case ISD::ADDC:
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case ISD::ADDC:
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@ -1,7 +1,6 @@
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;test for ADDC and ADDE expansion
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;test for ADDC and ADDE expansion
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;
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;
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; RUN: llvm-as < %s | llc -march=alpha
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; RUN: llvm-as < %s | llc -march=alpha
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; XFAIL: *
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define i128 @add128(i128 %x, i128 %y) {
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define i128 @add128(i128 %x, i128 %y) {
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entry:
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entry:
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9
test/CodeGen/Alpha/sub128.ll
Normal file
9
test/CodeGen/Alpha/sub128.ll
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@ -0,0 +1,9 @@
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;test for SUBC and SUBE expansion
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;
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; RUN: llvm-as < %s | llc -march=alpha
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define i128 @sub128(i128 %x, i128 %y) {
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entry:
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%tmp = sub i128 %y, %x
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ret i128 %tmp
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}
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