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Expand arith on machines without carry flags

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2008-10-07 14:15:42 +00:00
parent cb73d19a4c
commit 40d513960a
3 changed files with 42 additions and 10 deletions
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42
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -6431,7 +6431,6 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
break; break;
} }
} }
// Expand the subcomponents. // Expand the subcomponents.
SDValue LHSL, LHSH, RHSL, RHSH; SDValue LHSL, LHSH, RHSL, RHSH;
ExpandOp(Node->getOperand(0), LHSL, LHSH); ExpandOp(Node->getOperand(0), LHSL, LHSH);
@ -6442,16 +6441,41 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
LoOps[1] = RHSL; LoOps[1] = RHSL;
HiOps[0] = LHSH; HiOps[0] = LHSH;
HiOps[1] = RHSH; HiOps[1] = RHSH;
if (Node->getOpcode() == ISD::ADD) { if(TLI.isOperationLegal(ISD::ADDC, NVT)) {
Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); if (Node->getOpcode() == ISD::ADD) {
HiOps[2] = Lo.getValue(1); Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); HiOps[2] = Lo.getValue(1);
Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
} else {
Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
}
break;
} else { } else {
Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); if (Node->getOpcode() == ISD::ADD) {
HiOps[2] = Lo.getValue(1); Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
SDValue Cmp1 = DAG.getSetCC(NVT, Lo, LoOps[0], ISD::SETULT);
SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
DAG.getConstant(1, NVT),
DAG.getConstant(0, NVT));
SDValue Cmp2 = DAG.getSetCC(NVT, Lo, LoOps[1], ISD::SETULT);
SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
DAG.getConstant(1, NVT),
Carry1);
Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
} else {
Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
DAG.getConstant(1, NVT),
DAG.getConstant(0, NVT));
Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
}
break;
} }
break;
} }
case ISD::ADDC: case ISD::ADDC:

1
test/CodeGen/Alpha/add128.ll
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@ -1,7 +1,6 @@
;test for ADDC and ADDE expansion ;test for ADDC and ADDE expansion
; ;
; RUN: llvm-as < %s | llc -march=alpha ; RUN: llvm-as < %s | llc -march=alpha
; XFAIL: *
define i128 @add128(i128 %x, i128 %y) { define i128 @add128(i128 %x, i128 %y) {
entry: entry:

9
test/CodeGen/Alpha/sub128.ll Normal file
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@ -0,0 +1,9 @@
;test for SUBC and SUBE expansion
;
; RUN: llvm-as < %s | llc -march=alpha
define i128 @sub128(i128 %x, i128 %y) {
entry:
%tmp = sub i128 %y, %x
ret i128 %tmp
}