mirror of
https://github.com/RPCS3/llvm.git
synced 2025-02-15 16:28:48 +00:00
[Hexagon] Fix operand swapping in HexagonPeephole
Also, disable zero- and size-extend optimizations for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266821 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
9ebfa4db3c
commit
414bb96c93
@ -67,11 +67,11 @@ static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
|
||||
cl::desc("Disable Optimization of PNotP"));
|
||||
|
||||
static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
|
||||
cl::Hidden, cl::ZeroOrMore, cl::init(false),
|
||||
cl::Hidden, cl::ZeroOrMore, cl::init(true),
|
||||
cl::desc("Disable Optimization of Sign/Zero Extends"));
|
||||
|
||||
static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
|
||||
cl::Hidden, cl::ZeroOrMore, cl::init(false),
|
||||
cl::Hidden, cl::ZeroOrMore, cl::init(true),
|
||||
cl::desc("Disable Optimization of extensions to i64."));
|
||||
|
||||
namespace llvm {
|
||||
@ -308,6 +308,7 @@ void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
|
||||
case MachineOperand::MO_Register:
|
||||
if (Src.isReg()) {
|
||||
Dst.setReg(Src.getReg());
|
||||
Dst.setSubReg(Src.getSubReg());
|
||||
} else if (Src.isImm()) {
|
||||
Dst.ChangeToImmediate(Src.getImm());
|
||||
} else {
|
||||
@ -322,6 +323,7 @@ void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
|
||||
Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
|
||||
Src.isKill(), Src.isDead(), Src.isUndef(),
|
||||
Src.isDebug());
|
||||
Dst.setSubReg(Src.getSubReg());
|
||||
} else {
|
||||
llvm_unreachable("Unexpected src operand type");
|
||||
}
|
||||
|
30
test/CodeGen/Hexagon/peephole-op-swap.ll
Normal file
30
test/CodeGen/Hexagon/peephole-op-swap.ll
Normal file
@ -0,0 +1,30 @@
|
||||
; RUN: llc -march=hexagon < %s
|
||||
; REQUIRES: asserts
|
||||
|
||||
; The operand-swapping code in HexagonPeephole was not handling subregisters
|
||||
; correctly, resulting in a crash on this code.
|
||||
|
||||
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
|
||||
target triple = "hexagon"
|
||||
|
||||
@float_rounding_mode = external global i8, align 1
|
||||
@float_exception_flags = external global i8, align 1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i64 @fred(i32 %a) #0 {
|
||||
entry:
|
||||
br i1 undef, label %cleanup, label %lor.lhs.false
|
||||
|
||||
lor.lhs.false: ; preds = %entry
|
||||
%cmp3 = icmp eq i32 undef, 255
|
||||
%tobool4 = icmp ne i32 undef, 0
|
||||
%or.cond = and i1 %tobool4, %cmp3
|
||||
%. = select i1 %or.cond, i64 9223372036854775807, i64 -9223372036854775808
|
||||
br label %cleanup
|
||||
|
||||
cleanup: ; preds = %lor.lhs.false, %entry
|
||||
%retval.0 = phi i64 [ 9223372036854775807, %entry ], [ %., %lor.lhs.false ]
|
||||
ret i64 %retval.0
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
Loading…
x
Reference in New Issue
Block a user