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Missing piece of the ARM frame index post-scavenging conditionalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -944,6 +944,7 @@ bool ARMBaseRegisterInfo::
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requiresRegisterScavenging(const MachineFunction &MF) const {
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requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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return true;
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}
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}
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bool ARMBaseRegisterInfo::
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bool ARMBaseRegisterInfo::
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requiresFrameIndexScavenging(const MachineFunction &MF) const {
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requiresFrameIndexScavenging(const MachineFunction &MF) const {
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return ScavengeFrameIndexVals;
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return ScavengeFrameIndexVals;
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@ -77,6 +77,18 @@ Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
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return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
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return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
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}
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}
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bool
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Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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bool
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Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF)
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const {
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return true;
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}
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bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
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bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
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const MachineFrameInfo *FFI = MF.getFrameInfo();
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const MachineFrameInfo *FFI = MF.getFrameInfo();
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unsigned CFSize = FFI->getMaxCallFrameSize();
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unsigned CFSize = FFI->getMaxCallFrameSize();
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@ -40,6 +40,9 @@ public:
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const TargetRegisterClass *
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const TargetRegisterClass *
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getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
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bool hasReservedCallFrame(MachineFunction &MF) const;
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bool hasReservedCallFrame(MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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