mirror of
https://github.com/RPCS3/llvm.git
synced 2025-01-15 14:28:25 +00:00
Mark tBX as an indirect branch rather than a return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
ca93138e11
commit
421b106872
@ -1863,7 +1863,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tBX_RET_vararg);
|
||||
TmpInst.setOpcode(ARM::tBX);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
|
@ -361,14 +361,6 @@ def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
|
||||
//
|
||||
|
||||
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
|
||||
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
|
||||
T1Special<{1,1,0,?}> {
|
||||
// A6.2.3 & A8.6.25
|
||||
bits<4> Rm;
|
||||
let Inst{6-3} = Rm;
|
||||
let Inst{2-0} = 0b000;
|
||||
}
|
||||
|
||||
def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
|
||||
[(ARMretflag)]>,
|
||||
T1Special<{1,1,0,?}> {
|
||||
@ -391,6 +383,14 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
|
||||
|
||||
// Indirect branches
|
||||
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
||||
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
|
||||
T1Special<{1,1,0,?}> {
|
||||
// A6.2.3 & A8.6.25
|
||||
bits<4> Rm;
|
||||
let Inst{6-3} = Rm;
|
||||
let Inst{2-0} = 0b000;
|
||||
}
|
||||
|
||||
def tBRIND : TI<(outs), (ins GPR:$Rm),
|
||||
IIC_Br,
|
||||
"mov\tpc, $Rm",
|
||||
|
Loading…
x
Reference in New Issue
Block a user