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[X86] Remove sse2 intrinsic tests from the avx intrinsics test file.

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They are all covered by the SSE2 intrinsics test with SSE2, AVX, and AVX512 command lines.

Also remove an unneeded lfence intrinsic test since it was already covered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2017-02-21 07:32:11 +00:00
parent 3ba7715b43
commit 4228b1201f
5 changed files with 113 additions and 1223 deletions
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1186
test/CodeGen/X86/avx-intrinsics-x86.ll
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33
test/CodeGen/X86/avx-intrinsics-x86_64.ll
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@ -2,39 +2,6 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
; CHECK-LABEL: test_x86_sse2_cvtsd2si64:
; CHECK: ## BB#0:
; CHECK-NEXT: vcvtsd2si %xmm0, %rax
; CHECK-NEXT: retq
%res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
ret i64 %res
}
declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
; CHECK-LABEL: test_x86_sse2_cvtsi642sd:
; CHECK: ## BB#0:
; CHECK-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0
; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
; CHECK-LABEL: test_x86_sse2_cvttsd2si64:
; CHECK: ## BB#0:
; CHECK-NEXT: vcvttsd2si %xmm0, %rax
; CHECK-NEXT: retq
%res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
ret i64 %res
}
declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
define <4 x double> @test_x86_avx_vzeroall(<4 x double> %a, <4 x double> %b) {
; AVX-LABEL: test_x86_avx_vzeroall:
; AVX: ## BB#0:

8
test/CodeGen/X86/lfence.ll
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@ -1,8 +0,0 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep lfence
declare void @llvm.x86.sse2.lfence() nounwind
define void @test() {
call void @llvm.x86.sse2.lfence()
ret void
}

31
test/CodeGen/X86/sse2-intrinsics-x86.ll
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@ -1712,3 +1712,34 @@ define void @test_x86_sse2_pause() {
ret void
}
declare void @llvm.x86.sse2.pause() nounwind
define void @lfence() nounwind {
; CHECK-LABEL: lfence:
; CHECK: ## BB#0:
; CHECK-NEXT: lfence ## encoding: [0x0f,0xae,0xe8]
; CHECK-NEXT: retl ## encoding: [0xc3]
tail call void @llvm.x86.sse2.lfence()
ret void
}
declare void @llvm.x86.sse2.lfence() nounwind
define void @mfence() nounwind {
; CHECK-LABEL: mfence:
; CHECK: ## BB#0:
; CHECK-NEXT: mfence ## encoding: [0x0f,0xae,0xf0]
; CHECK-NEXT: retl ## encoding: [0xc3]
tail call void @llvm.x86.sse2.mfence()
ret void
}
declare void @llvm.x86.sse2.mfence() nounwind
define void @clflush(i8* %p) nounwind {
; CHECK-LABEL: clflush:
; CHECK: ## BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; CHECK-NEXT: clflush (%eax) ## encoding: [0x0f,0xae,0x38]
; CHECK-NEXT: retl ## encoding: [0xc3]
tail call void @llvm.x86.sse2.clflush(i8* %p)
ret void
}
declare void @llvm.x86.sse2.clflush(i8*) nounwind

78
test/CodeGen/X86/sse2-intrinsics-x86_64.ll Normal file
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@ -0,0 +1,78 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -show-mc-encoding | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx2 -show-mc-encoding | FileCheck %s --check-prefix=VCHECK --check-prefix=AVX2
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=VCHECK --check-prefix=SKX
define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
; CHECK-LABEL: test_x86_sse2_cvtsd2si64:
; CHECK: ## BB#0:
; CHECK-NEXT: vcvtsd2si %xmm0, %rax
; CHECK-NEXT: retq
; SSE-LABEL: test_x86_sse2_cvtsd2si64:
; SSE: ## BB#0:
; SSE-NEXT: cvtsd2si %xmm0, %rax ## encoding: [0xf2,0x48,0x0f,0x2d,0xc0]
; SSE-NEXT: retq ## encoding: [0xc3]
;
; AVX2-LABEL: test_x86_sse2_cvtsd2si64:
; AVX2: ## BB#0:
; AVX2-NEXT: vcvtsd2si %xmm0, %rax ## encoding: [0xc4,0xe1,0xfb,0x2d,0xc0]
; AVX2-NEXT: retq ## encoding: [0xc3]
;
; SKX-LABEL: test_x86_sse2_cvtsd2si64:
; SKX: ## BB#0:
; SKX-NEXT: vcvtsd2si %xmm0, %rax ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfb,0x2d,0xc0]
; SKX-NEXT: retq ## encoding: [0xc3]
%res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
ret i64 %res
}
declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
; CHECK-LABEL: test_x86_sse2_cvtsi642sd:
; CHECK: ## BB#0:
; CHECK-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0
; CHECK-NEXT: retq
; SSE-LABEL: test_x86_sse2_cvtsi642sd:
; SSE: ## BB#0:
; SSE-NEXT: cvtsi2sdq %rdi, %xmm0 ## encoding: [0xf2,0x48,0x0f,0x2a,0xc7]
; SSE-NEXT: retq ## encoding: [0xc3]
;
; AVX2-LABEL: test_x86_sse2_cvtsi642sd:
; AVX2: ## BB#0:
; AVX2-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 ## encoding: [0xc4,0xe1,0xfb,0x2a,0xc7]
; AVX2-NEXT: retq ## encoding: [0xc3]
;
; SKX-LABEL: test_x86_sse2_cvtsi642sd:
; SKX: ## BB#0:
; SKX-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xff,0x08,0x2a,0xc7]
; SKX-NEXT: retq ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
; CHECK-LABEL: test_x86_sse2_cvttsd2si64:
; CHECK: ## BB#0:
; CHECK-NEXT: vcvttsd2si %xmm0, %rax
; CHECK-NEXT: retq
; SSE-LABEL: test_x86_sse2_cvttsd2si64:
; SSE: ## BB#0:
; SSE-NEXT: cvttsd2si %xmm0, %rax ## encoding: [0xf2,0x48,0x0f,0x2c,0xc0]
; SSE-NEXT: retq ## encoding: [0xc3]
;
; AVX2-LABEL: test_x86_sse2_cvttsd2si64:
; AVX2: ## BB#0:
; AVX2-NEXT: vcvttsd2si %xmm0, %rax ## encoding: [0xc4,0xe1,0xfb,0x2c,0xc0]
; AVX2-NEXT: retq ## encoding: [0xc3]
;
; SKX-LABEL: test_x86_sse2_cvttsd2si64:
; SKX: ## BB#0:
; SKX-NEXT: vcvttsd2si %xmm0, %rax ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfb,0x2c,0xc0]
; SKX-NEXT: retq ## encoding: [0xc3]
%res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
ret i64 %res
}
declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone