RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-27 05:32:22 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Remove some unnecessary code. The conditions it was checking had already been ruled out by the caller.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201039 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-02-09 07:13:41 +00:00
parent 12ea35fc6a
commit 426497e2fb
1 changed files with 0 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
utils/TableGen/FixedLenDecoderEmitter.cpp
View File

@ -1705,13 +1705,6 @@ static bool populateInstruction(CodeGenTarget &Target,
// If all the bit positions are not specified; do not decode this instruction. // If all the bit positions are not specified; do not decode this instruction.
// We are bound to fail! For proper disassembly, the well-known encoding bits // We are bound to fail! For proper disassembly, the well-known encoding bits
// of the instruction must be fully specified. // of the instruction must be fully specified.
//
// This also removes pseudo instructions from considerations of disassembly,
// which is a better design and less fragile than the name matchings.
// Ignore "asm parser only" instructions.
if (Def.getValueAsBit("isAsmParserOnly") ||
Def.getValueAsBit("isCodeGenOnly"))
return false;
BitsInit &Bits = getBitsField(Def, "Inst"); BitsInit &Bits = getBitsField(Def, "Inst");
if (Bits.allInComplete()) return false; if (Bits.allInComplete()) return false;