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Remove the caching of the target machine from SystemZTargetLowering.
Update all callers and uses accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211880 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
d023a353c1
commit
4299a8b4ba
@ -82,7 +82,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
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SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
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: TargetLowering(tm, new TargetLoweringObjectFileELF()),
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Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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Subtarget(*tm.getSubtargetImpl()) {
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MVT PtrVT = getPointerTy();
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// Set up the register classes.
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@ -673,11 +673,13 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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MachineRegisterInfo &MRI = MF.getRegInfo();
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SystemZMachineFunctionInfo *FuncInfo =
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MF.getInfo<SystemZMachineFunctionInfo>();
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auto *TFL = static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
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auto *TFL = static_cast<const SystemZFrameLowering *>(
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DAG.getTarget().getFrameLowering());
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
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CCState CCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
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*DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
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unsigned NumFixedGPRs = 0;
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@ -815,7 +817,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
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// Analyze the operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
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CCState ArgCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
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*DAG.getContext());
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ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
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// We don't support GuaranteedTailCallOpt, only automatically-detected
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@ -931,7 +934,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RetLocs;
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CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
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CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
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*DAG.getContext());
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RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
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// Copy all of the result registers out of their specified physreg.
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@ -962,7 +966,8 @@ SystemZTargetLowering::LowerReturn(SDValue Chain,
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// Assign locations to each returned value.
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SmallVector<CCValAssign, 16> RetLocs;
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CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
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CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
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*DAG.getContext());
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RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
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// Quick exit for void returns
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@ -1786,8 +1791,8 @@ SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
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const GlobalValue *GV = Node->getGlobal();
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int64_t Offset = Node->getOffset();
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EVT PtrVT = getPointerTy();
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Reloc::Model RM = TM.getRelocationModel();
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CodeModel::Model CM = TM.getCodeModel();
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Reloc::Model RM = DAG.getTarget().getRelocationModel();
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CodeModel::Model CM = DAG.getTarget().getCodeModel();
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SDValue Result;
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if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
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@ -1824,7 +1829,7 @@ SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
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SDLoc DL(Node);
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const GlobalValue *GV = Node->getGlobal();
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EVT PtrVT = getPointerTy();
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TLSModel::Model model = TM.getTLSModel(GV);
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TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
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if (model != TLSModel::LocalExec)
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llvm_unreachable("only local-exec TLS mode supported");
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@ -2287,9 +2292,9 @@ SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
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// Use an addition if the operand is constant and either LAA(G) is
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// available or the negative value is in the range of A(G)FHI.
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int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
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if (isInt<32>(Value) || TM.getSubtargetImpl()->hasInterlockedAccess1())
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if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
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NegSrc2 = DAG.getConstant(Value, MemVT);
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} else if (TM.getSubtargetImpl()->hasInterlockedAccess1())
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} else if (Subtarget.hasInterlockedAccess1())
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// Use LAA(G) if available.
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NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
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Src2);
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@ -2602,7 +2607,8 @@ static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
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MachineBasicBlock *
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SystemZTargetLowering::emitSelect(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
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MBB->getParent()->getTarget().getInstrInfo());
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned TrueReg = MI->getOperand(1).getReg();
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@ -2650,7 +2656,8 @@ SystemZTargetLowering::emitCondStore(MachineInstr *MI,
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MachineBasicBlock *MBB,
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unsigned StoreOpcode, unsigned STOCOpcode,
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bool Invert) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
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MBB->getParent()->getTarget().getInstrInfo());
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unsigned SrcReg = MI->getOperand(0).getReg();
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MachineOperand Base = MI->getOperand(1);
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@ -2665,7 +2672,7 @@ SystemZTargetLowering::emitCondStore(MachineInstr *MI,
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// Use STOCOpcode if possible. We could use different store patterns in
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// order to avoid matching the index register, but the performance trade-offs
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// might be more complicated in that case.
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if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
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if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
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if (Invert)
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CCMask ^= CCValid;
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BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
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@ -2717,8 +2724,9 @@ SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
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unsigned BinOpcode,
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unsigned BitSize,
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bool Invert) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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MachineFunction &MF = *MBB->getParent();
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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bool IsSubWord = (BitSize < 32);
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@ -2840,8 +2848,9 @@ SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
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unsigned CompareOpcode,
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unsigned KeepOldMask,
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unsigned BitSize) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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MachineFunction &MF = *MBB->getParent();
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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bool IsSubWord = (BitSize < 32);
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@ -2951,8 +2960,9 @@ SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
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MachineBasicBlock *
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SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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MachineFunction &MF = *MBB->getParent();
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Extract the operands. Base can be a register or a frame index.
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@ -3067,8 +3077,9 @@ MachineBasicBlock *
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SystemZTargetLowering::emitExt128(MachineInstr *MI,
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MachineBasicBlock *MBB,
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bool ClearEven, unsigned SubReg) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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MachineFunction &MF = *MBB->getParent();
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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DebugLoc DL = MI->getDebugLoc();
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@ -3098,8 +3109,9 @@ MachineBasicBlock *
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SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
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MachineBasicBlock *MBB,
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unsigned Opcode) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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MachineFunction &MF = *MBB->getParent();
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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DebugLoc DL = MI->getDebugLoc();
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@ -3267,8 +3279,9 @@ MachineBasicBlock *
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SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
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MachineBasicBlock *MBB,
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unsigned Opcode) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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MachineFunction &MF = *MBB->getParent();
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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DebugLoc DL = MI->getDebugLoc();
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@ -249,7 +249,6 @@ public:
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private:
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const SystemZSubtarget &Subtarget;
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const SystemZTargetMachine &TM;
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// Implement LowerOperation for individual opcodes.
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SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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