RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-26 04:34:41 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

R0 is a sub-register of X0, etc.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36939 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-08 17:03:51 +00:00
parent 1cc0096d55
commit 43182ac0d6
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/PowerPC/PPCRegisterInfo.td
View File

@ -22,9 +22,9 @@ class GPR<bits<5> num, string n> : PPCReg<n> {
}
// GP8 - One of the 32 64-bit general-purpose registers
class GP8<GPR Alias> : PPCReg<Alias.Name> {
field bits<5> Num = Alias.Num;
let Aliases = [Alias];
class GP8<GPR SubReg> : PPCReg<SubReg.Name> {
field bits<5> Num = SubReg.Num;
let SubRegs = [SubReg];
}
// SPR - One of the 32-bit special-purpose registers