RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-02 08:46:37 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Constant fold SIGN_EXTEND_INREG with ashr not lshr.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47992 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-03-06 08:20:51 +00:00
parent 819a66cf25
commit 433f6f62ca
2 changed files with 15 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2029,7 +2029,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
APInt Val = N1C->getAPIntValue(); APInt Val = N1C->getAPIntValue();
unsigned FromBits = MVT::getSizeInBits(cast<VTSDNode>(N2)->getVT()); unsigned FromBits = MVT::getSizeInBits(cast<VTSDNode>(N2)->getVT());
Val <<= Val.getBitWidth()-FromBits; Val <<= Val.getBitWidth()-FromBits;
Val = Val.lshr(Val.getBitWidth()-FromBits); Val = Val.ashr(Val.getBitWidth()-FromBits);
return getConstant(Val, VT); return getConstant(Val, VT);
} }
break; break;

14
test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll Normal file
View File

@ -0,0 +1,14 @@
; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | not grep 255
define i32 @main(i32 %argc, i8** %argv) {
entry:
br label %bb1
bb1: ; preds = %entry
%tmp3.i.i = load i8* null, align 1 ; <i8> [#uses=1]
%tmp4.i.i = icmp slt i8 %tmp3.i.i, 0 ; <i1> [#uses=1]
br i1 %tmp4.i.i, label %bb2, label %bb3
bb2: ; preds = %bb1
ret i32 1
bb3: ; preds = %bb1
ret i32 0
}