mirror of
https://github.com/RPCS3/llvm.git
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[AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289282 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eugene Zelenko
parent
684e0cf956
commit
43dec7d682
@ -10,23 +10,22 @@
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// Interface to describe a layout of a stack frame on a AMDGPU target machine.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUFrameLowering.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, unsigned StackAl,
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int LAO, unsigned TransAl)
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: TargetFrameLowering(D, StackAl, LAO, TransAl) { }
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AMDGPUFrameLowering::~AMDGPUFrameLowering() { }
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AMDGPUFrameLowering::~AMDGPUFrameLowering() = default;
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unsigned AMDGPUFrameLowering::getStackWidth(const MachineFunction &MF) const {
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// XXX: Hardcoding to 1 for now.
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//
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// I think the StackWidth should stored as metadata associated with the
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@ -101,4 +100,3 @@ int AMDGPUFrameLowering::getFrameIndexReference(const MachineFunction &MF,
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return OffsetBytes / (getStackWidth(MF) * 4);
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}
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@ -11,6 +11,7 @@
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/// \brief Interface to describe a layout of a stack frame on an AMDGPU target.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUFRAMELOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUFRAMELOWERING_H
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@ -27,7 +28,7 @@ class AMDGPUFrameLowering : public TargetFrameLowering {
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public:
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AMDGPUFrameLowering(StackDirection D, unsigned StackAl, int LAO,
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unsigned TransAl = 1);
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virtual ~AMDGPUFrameLowering();
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~AMDGPUFrameLowering() override;
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/// \returns The number of 32-bit sub-registers that are used when storing
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/// values to the stack.
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@ -40,5 +41,7 @@ public:
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return false;
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}
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};
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} // namespace llvm
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#endif
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUFRAMELOWERING_H
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@ -12,25 +12,48 @@
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUIntrinsicInfo.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUISelLowering.h" // For AMDGPUISD
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#include "AMDGPUSubtarget.h"
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#include "SIDefines.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "SIISelLowering.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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#include <cstdint>
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#include <new>
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#include <vector>
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using namespace llvm;
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namespace llvm {
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class R600InstrInfo;
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}
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} // end namespace llvm
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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@ -48,8 +71,8 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
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public:
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explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel) {}
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~AMDGPUDAGToDAGISel() override = default;
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virtual ~AMDGPUDAGToDAGISel();
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bool runOnMachineFunction(MachineFunction &MF) override;
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void Select(SDNode *N) override;
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StringRef getPassName() const override;
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@ -149,6 +172,7 @@ private:
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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};
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} // end anonymous namespace
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/// \brief This pass converts a legalized DAG into a AMDGPU-specific
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@ -163,9 +187,6 @@ bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
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}
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bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const {
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const SIInstrInfo *TII
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= static_cast<const SISubtarget *>(Subtarget)->getInstrInfo();
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@ -902,7 +923,6 @@ bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
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Ptr = N2;
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VAddr = N3;
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} else {
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// (add N0, C1) -> offset
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VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
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Ptr = N0;
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@ -1205,7 +1225,6 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
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bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
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SDValue &Offset, bool &Imm) const {
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SDLoc SL(Addr);
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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SDValue N0 = Addr.getOperand(0);
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@ -1451,7 +1470,6 @@ void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
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CurDAG->SelectNodeTo(N, AMDGPU::S_CBRANCH_VCCNZ, MVT::Other,
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N->getOperand(2), // Basic Block
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VCC.getValue(0));
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return;
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}
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// This is here because there isn't a way to use the generated sub0_sub1 as the
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@ -1522,7 +1540,6 @@ void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
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bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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unsigned Mods = 0;
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Src = In;
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@ -23,16 +23,22 @@
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#include "SIISelLowering.h"
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#include "SIFrameLowering.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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#include <cstdint>
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#include <memory>
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#include <utility>
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#define GET_SUBTARGETINFO_HEADER
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#include "AMDGPUGenSubtargetInfo.inc"
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namespace llvm {
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class SIMachineFunctionInfo;
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class StringRef;
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class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
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@ -125,7 +131,8 @@ protected:
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public:
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AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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const TargetMachine &TM);
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virtual ~AMDGPUSubtarget();
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~AMDGPUSubtarget() override;
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AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef GPU, StringRef FS);
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@ -595,6 +602,6 @@ public:
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unsigned getMaxNumSGPRs() const;
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};
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} // End namespace llvm
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} // end namespace llvm
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#endif
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
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@ -17,6 +17,13 @@
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#include "AMDGPUIntrinsicInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetMachine.h"
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#include <memory>
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namespace llvm {
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@ -37,7 +44,7 @@ public:
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StringRef FS, TargetOptions Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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~AMDGPUTargetMachine();
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~AMDGPUTargetMachine() override;
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const AMDGPUSubtarget *getSubtargetImpl() const;
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const AMDGPUSubtarget *getSubtargetImpl(const Function &) const override = 0;
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@ -91,6 +98,6 @@ public:
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const SISubtarget *getSubtargetImpl(const Function &) const override;
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};
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} // End namespace llvm
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} // end namespace llvm
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#endif
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
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@ -15,30 +15,45 @@
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#include "Utils/AMDKernelCodeTUtils.h"
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#include "Utils/AMDGPUAsmUtils.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCAsmParserExtension.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCParser/MCTargetAsmParser.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbolELF.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/SMLoc.h"
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#include "llvm/Support/TargetRegistry.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <cstring>
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#include <iterator>
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#include <map>
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#include <memory>
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#include <string>
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#include <vector>
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using namespace llvm;
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using namespace llvm::AMDGPU;
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@ -46,7 +61,6 @@ using namespace llvm::AMDGPU;
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namespace {
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class AMDGPUAsmParser;
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struct OptionalOperand;
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enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_TTMP, IS_SPECIAL };
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@ -365,7 +379,6 @@ public:
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return S->getSymbol().getName();
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}
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StringRef getToken() const {
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assert(isToken());
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@ -715,13 +728,15 @@ public:
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//bool ProcessInstruction(MCInst &Inst);
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OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int);
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OperandMatchResultTy parseIntWithPrefix(const char *Prefix,
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OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
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bool (*ConvertResult)(int64_t&) = 0);
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OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);
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OperandMatchResultTy parseStringWithPrefix(StringRef Prefix, StringRef &Value);
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OperandMatchResultTy
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parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
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bool (*ConvertResult)(int64_t &) = nullptr);
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OperandMatchResultTy
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parseNamedBit(const char *Name, OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);
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OperandMatchResultTy parseStringWithPrefix(StringRef Prefix,
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StringRef &Value);
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OperandMatchResultTy parseImm(OperandVector &Operands);
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OperandMatchResultTy parseRegOrImm(OperandVector &Operands);
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@ -808,6 +823,8 @@ struct OptionalOperand {
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bool (*ConvertResult)(int64_t&);
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};
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} // end anonymous namespace
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// May be called with integer type with equivalent bitwidth.
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static const fltSemantics *getFltSemantics(MVT VT) {
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switch (VT.getSizeInBits()) {
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@ -822,8 +839,6 @@ static const fltSemantics *getFltSemantics(MVT VT) {
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Operand
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//===----------------------------------------------------------------------===//
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@ -1556,7 +1571,6 @@ bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {
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}
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bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
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uint32_t Major;
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uint32_t Minor;
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uint32_t Stepping;
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@ -1573,7 +1587,6 @@ bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
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return false;
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}
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if (ParseDirectiveMajorMinor(Major, Minor))
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return true;
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@ -1624,12 +1637,10 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
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}
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bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
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amd_kernel_code_t Header;
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AMDGPU::initDefaultAMDKernelCodeT(Header, getSTI().getFeatureBits());
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while (true) {
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// Lex EndOfStatement. This is in a while loop, because lexing a comment
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// will set the current token to EndOfStatement.
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while(getLexer().is(AsmToken::EndOfStatement))
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@ -1998,7 +2009,6 @@ AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) {
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void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
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const OperandVector &Operands) {
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OptionalImmIndexMap OptionalIdx;
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for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
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@ -2022,7 +2032,6 @@ void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
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}
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void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
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std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
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bool GDSOnly = false;
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@ -2517,7 +2526,7 @@ AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {
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}
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Imm16Val |= (StreamId << STREAM_ID_SHIFT_);
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}
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} while (0);
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} while (false);
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}
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break;
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}
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@ -3224,24 +3233,24 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
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if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa) {
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// V_NOP_sdwa has no optional sdwa arguments
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switch (BasicInstType) {
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case SIInstrFlags::VOP1: {
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case SIInstrFlags::VOP1:
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
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break;
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}
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case SIInstrFlags::VOP2: {
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case SIInstrFlags::VOP2:
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
|
||||
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
|
||||
break;
|
||||
}
|
||||
case SIInstrFlags::VOPC: {
|
||||
|
||||
case SIInstrFlags::VOPC:
|
||||
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
|
||||
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
|
||||
}
|
||||
@ -3269,7 +3278,6 @@ extern "C" void LLVMInitializeAMDGPUAsmParser() {
|
||||
#define GET_MATCHER_IMPLEMENTATION
|
||||
#include "AMDGPUGenAsmMatcher.inc"
|
||||
|
||||
|
||||
// This fuction should be defined after auto-generated include so that we have
|
||||
// MatchClassKind enum defined
|
||||
unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
|
||||
|
||||
@ -18,7 +18,11 @@
|
||||
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
|
||||
#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
|
||||
#include "llvm/MC/MCDisassembler/MCSymbolizer.h"
|
||||
#include <cstdint>
|
||||
#include <algorithm>
|
||||
#include <memory>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
@ -40,7 +44,7 @@ public:
|
||||
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
|
||||
MCDisassembler(STI, Ctx) {}
|
||||
|
||||
~AMDGPUDisassembler() {}
|
||||
~AMDGPUDisassembler() override = default;
|
||||
|
||||
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
|
||||
ArrayRef<uint8_t> Bytes, uint64_t Address,
|
||||
@ -52,7 +56,7 @@ public:
|
||||
MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
|
||||
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
|
||||
|
||||
MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
|
||||
MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
|
||||
|
||||
DecodeStatus tryDecodeInst(const uint8_t* Table,
|
||||
MCInst &MI,
|
||||
@ -82,6 +86,7 @@ public:
|
||||
OPW_LAST_,
|
||||
OPW_FIRST_ = OPW32
|
||||
};
|
||||
|
||||
unsigned getVgprClassId(const OpWidthTy Width) const;
|
||||
unsigned getSgprClassId(const OpWidthTy Width) const;
|
||||
unsigned getTtmpClassId(const OpWidthTy Width) const;
|
||||
@ -118,6 +123,6 @@ public:
|
||||
uint64_t Address) override;
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
} // end namespace llvm
|
||||
|
||||
#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
|
||||
#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
|
||||
|
||||
@ -19,12 +19,14 @@ public:
|
||||
R600FrameLowering(StackDirection D, unsigned StackAl, int LAO,
|
||||
unsigned TransAl = 1) :
|
||||
AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
|
||||
virtual ~R600FrameLowering();
|
||||
~R600FrameLowering() override;
|
||||
|
||||
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const {}
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {}
|
||||
void emitPrologue(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const override {}
|
||||
void emitEpilogue(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const override {}
|
||||
};
|
||||
|
||||
}
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_LIB_TARGET_AMDGPU_R600FRAMELOWERING_H
|
||||
|
||||
@ -17,16 +17,36 @@
|
||||
#include "AMDGPUIntrinsicInfo.h"
|
||||
#include "AMDGPUSubtarget.h"
|
||||
#include "R600Defines.h"
|
||||
#include "R600FrameLowering.h"
|
||||
#include "R600InstrInfo.h"
|
||||
#include "R600MachineFunctionInfo.h"
|
||||
#include "llvm/Analysis/ValueTracking.h"
|
||||
#include "Utils/AMDGPUBaseInfo.h"
|
||||
#include "llvm/ADT/APFloat.h"
|
||||
#include "llvm/ADT/APInt.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/CallingConvLower.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/DAGCombine.h"
|
||||
#include "llvm/CodeGen/ISDOpcodes.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineMemOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineValueType.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/IR/Argument.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/Constants.h"
|
||||
#include "llvm/IR/DerivedTypes.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <iterator>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -72,7 +92,6 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
|
||||
setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
|
||||
setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
|
||||
|
||||
|
||||
setOperationAction(ISD::STORE, MVT::i8, Custom);
|
||||
setOperationAction(ISD::STORE, MVT::i32, Custom);
|
||||
setOperationAction(ISD::STORE, MVT::v2i32, Custom);
|
||||
@ -192,7 +211,6 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
|
||||
|
||||
setSchedulingPreference(Sched::Source);
|
||||
|
||||
|
||||
setTargetDAGCombine(ISD::FP_ROUND);
|
||||
setTargetDAGCombine(ISD::FP_TO_SINT);
|
||||
setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
|
||||
@ -214,7 +232,7 @@ static inline bool isEOP(MachineBasicBlock::iterator I) {
|
||||
MachineBasicBlock *
|
||||
R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
MachineFunction * MF = BB->getParent();
|
||||
MachineFunction *MF = BB->getParent();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
MachineBasicBlock::iterator I = MI;
|
||||
const R600InstrInfo *TII = getSubtarget()->getInstrInfo();
|
||||
@ -281,10 +299,12 @@ R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
||||
.bitcastToAPInt()
|
||||
.getZExtValue());
|
||||
break;
|
||||
|
||||
case AMDGPU::MOV_IMM_I32:
|
||||
TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(),
|
||||
MI.getOperand(1).getImm());
|
||||
break;
|
||||
|
||||
case AMDGPU::MOV_IMM_GLOBAL_ADDR: {
|
||||
//TODO: Perhaps combine this instruction with the next if possible
|
||||
auto MIB = TII->buildDefaultInstruction(
|
||||
@ -294,6 +314,7 @@ R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
||||
MIB->getOperand(Idx) = MI.getOperand(1);
|
||||
break;
|
||||
}
|
||||
|
||||
case AMDGPU::CONST_COPY: {
|
||||
MachineInstr *NewMI = TII->buildDefaultInstruction(
|
||||
*BB, MI, AMDGPU::MOV, MI.getOperand(0).getReg(), AMDGPU::ALU_CONST);
|
||||
@ -304,21 +325,21 @@ R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
||||
|
||||
case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
|
||||
case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
|
||||
case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
|
||||
case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
|
||||
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
|
||||
.addOperand(MI.getOperand(0))
|
||||
.addOperand(MI.getOperand(1))
|
||||
.addImm(isEOP(I)); // Set End of program bit
|
||||
break;
|
||||
}
|
||||
case AMDGPU::RAT_STORE_TYPED_eg: {
|
||||
|
||||
case AMDGPU::RAT_STORE_TYPED_eg:
|
||||
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
|
||||
.addOperand(MI.getOperand(0))
|
||||
.addOperand(MI.getOperand(1))
|
||||
.addOperand(MI.getOperand(2))
|
||||
.addImm(isEOP(I)); // Set End of program bit
|
||||
break;
|
||||
}
|
||||
|
||||
case AMDGPU::BRANCH:
|
||||
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
|
||||
.addOperand(MI.getOperand(0));
|
||||
@ -619,14 +640,12 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
|
||||
|
||||
SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
|
||||
SDValue Vector) const {
|
||||
|
||||
SDLoc DL(Vector);
|
||||
EVT VecVT = Vector.getValueType();
|
||||
EVT EltVT = VecVT.getVectorElementType();
|
||||
SmallVector<SDValue, 8> Args;
|
||||
|
||||
for (unsigned i = 0, e = VecVT.getVectorNumElements();
|
||||
i != e; ++i) {
|
||||
for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) {
|
||||
Args.push_back(DAG.getNode(
|
||||
ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector,
|
||||
DAG.getConstant(i, DL, getVectorIdxTy(DAG.getDataLayout()))));
|
||||
@ -637,7 +656,6 @@ SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
|
||||
|
||||
SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
|
||||
SDLoc DL(Op);
|
||||
SDValue Vector = Op.getOperand(0);
|
||||
SDValue Index = Op.getOperand(1);
|
||||
@ -671,7 +689,6 @@ SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
|
||||
SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
|
||||
SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
|
||||
GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
|
||||
if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
|
||||
return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
|
||||
@ -1130,7 +1147,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
// Private AS needs special fixes
|
||||
if (Align < MemVT.getStoreSize() && (AS != AMDGPUAS::PRIVATE_ADDRESS) &&
|
||||
!allowsMisalignedMemoryAccesses(MemVT, AS, Align, NULL)) {
|
||||
!allowsMisalignedMemoryAccesses(MemVT, AS, Align, nullptr)) {
|
||||
return expandUnalignedStore(StoreNode, DAG);
|
||||
}
|
||||
|
||||
@ -1710,7 +1727,6 @@ SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4],
|
||||
return BuildVector;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Custom DAG Optimizations
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2022,7 +2038,6 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
|
||||
unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
|
||||
uint64_t ImmValue = 0;
|
||||
|
||||
|
||||
if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
|
||||
ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
|
||||
float FloatValue = FPC->getValueAPF().convertToFloat();
|
||||
|
||||
@ -16,6 +16,7 @@
|
||||
#define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
|
||||
|
||||
#include "llvm/CodeGen/MachineScheduler.h"
|
||||
#include <vector>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -25,10 +26,10 @@ class R600InstrInfo;
|
||||
struct R600RegisterInfo;
|
||||
|
||||
class R600SchedStrategy final : public MachineSchedStrategy {
|
||||
const ScheduleDAGMILive *DAG;
|
||||
const R600InstrInfo *TII;
|
||||
const R600RegisterInfo *TRI;
|
||||
MachineRegisterInfo *MRI;
|
||||
const ScheduleDAGMILive *DAG = nullptr;
|
||||
const R600InstrInfo *TII = nullptr;
|
||||
const R600RegisterInfo *TRI = nullptr;
|
||||
MachineRegisterInfo *MRI = nullptr;
|
||||
|
||||
enum InstKind {
|
||||
IDAlu,
|
||||
@ -66,11 +67,8 @@ class R600SchedStrategy final : public MachineSchedStrategy {
|
||||
int OccupedSlotsMask;
|
||||
|
||||
public:
|
||||
R600SchedStrategy() :
|
||||
DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
|
||||
}
|
||||
|
||||
virtual ~R600SchedStrategy() {}
|
||||
R600SchedStrategy() = default;
|
||||
~R600SchedStrategy() override = default;
|
||||
|
||||
void initialize(ScheduleDAGMI *dag) override;
|
||||
SUnit *pickNode(bool &IsTopNode) override;
|
||||
@ -97,6 +95,6 @@ private:
|
||||
void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
} // end namespace llvm
|
||||
|
||||
#endif /* R600MACHINESCHEDULER_H_ */
|
||||
#endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
#include "AMDGPUFrameLowering.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class SIInstrInfo;
|
||||
class SIMachineFunctionInfo;
|
||||
class SIRegisterInfo;
|
||||
@ -23,7 +24,7 @@ public:
|
||||
SIFrameLowering(StackDirection D, unsigned StackAl, int LAO,
|
||||
unsigned TransAl = 1) :
|
||||
AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
|
||||
~SIFrameLowering() override {}
|
||||
~SIFrameLowering() override = default;
|
||||
|
||||
void emitPrologue(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const override;
|
||||
@ -58,6 +59,6 @@ private:
|
||||
void emitDebuggerPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||
};
|
||||
|
||||
}
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- SIMachineScheduler.h - SI Scheduler Interface -*- C++ -*-------===//
|
||||
//===-- SIMachineScheduler.h - SI Scheduler Interface -----------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -16,10 +16,16 @@
|
||||
#define LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
|
||||
|
||||
#include "SIInstrInfo.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineScheduler.h"
|
||||
#include "llvm/CodeGen/RegisterPressure.h"
|
||||
|
||||
using namespace llvm;
|
||||
#include "llvm/CodeGen/ScheduleDAG.h"
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <map>
|
||||
#include <memory>
|
||||
#include <set>
|
||||
#include <vector>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
@ -93,12 +99,10 @@ class SIScheduleBlock {
|
||||
public:
|
||||
SIScheduleBlock(SIScheduleDAGMI *DAG, SIScheduleBlockCreator *BC,
|
||||
unsigned ID):
|
||||
DAG(DAG), BC(BC), SUnits(), TopReadySUs(), ScheduledSUnits(),
|
||||
TopRPTracker(TopPressure), Scheduled(false),
|
||||
HighLatencyBlock(false), ID(ID),
|
||||
Preds(), Succs(), NumHighLatencySuccessors(0) {};
|
||||
DAG(DAG), BC(BC), TopRPTracker(TopPressure), Scheduled(false),
|
||||
HighLatencyBlock(false), ID(ID), NumHighLatencySuccessors(0) {}
|
||||
|
||||
~SIScheduleBlock() {};
|
||||
~SIScheduleBlock() = default;
|
||||
|
||||
unsigned getID() const { return ID; }
|
||||
|
||||
@ -146,7 +150,6 @@ public:
|
||||
|
||||
bool isScheduled() { return Scheduled; }
|
||||
|
||||
|
||||
// Needs the block to be scheduled inside
|
||||
// TODO: find a way to compute it.
|
||||
std::vector<unsigned> &getInternalAdditionnalRegUsage() {
|
||||
@ -161,7 +164,7 @@ public:
|
||||
private:
|
||||
struct SISchedCandidate : SISchedulerCandidate {
|
||||
// The best SUnit candidate.
|
||||
SUnit *SU;
|
||||
SUnit *SU = nullptr;
|
||||
|
||||
unsigned SGPRUsage;
|
||||
unsigned VGPRUsage;
|
||||
@ -169,8 +172,7 @@ private:
|
||||
unsigned LowLatencyOffset;
|
||||
bool HasLowLatencyNonWaitedParent;
|
||||
|
||||
SISchedCandidate()
|
||||
: SU(nullptr) {}
|
||||
SISchedCandidate() = default;
|
||||
|
||||
bool isValid() const { return SU; }
|
||||
|
||||
@ -341,17 +343,17 @@ public:
|
||||
SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
|
||||
SISchedulerBlockSchedulerVariant Variant,
|
||||
SIScheduleBlocks BlocksStruct);
|
||||
~SIScheduleBlockScheduler() {};
|
||||
~SIScheduleBlockScheduler() = default;
|
||||
|
||||
std::vector<SIScheduleBlock*> getBlocks() { return BlocksScheduled; };
|
||||
std::vector<SIScheduleBlock*> getBlocks() { return BlocksScheduled; }
|
||||
|
||||
unsigned getVGPRUsage() { return maxVregUsage; };
|
||||
unsigned getSGPRUsage() { return maxSregUsage; };
|
||||
unsigned getVGPRUsage() { return maxVregUsage; }
|
||||
unsigned getSGPRUsage() { return maxSregUsage; }
|
||||
|
||||
private:
|
||||
struct SIBlockSchedCandidate : SISchedulerCandidate {
|
||||
// The best Block candidate.
|
||||
SIScheduleBlock *Block;
|
||||
SIScheduleBlock *Block = nullptr;
|
||||
|
||||
bool IsHighLatency;
|
||||
int VGPRUsageDiff;
|
||||
@ -360,8 +362,7 @@ private:
|
||||
unsigned LastPosHighLatParentScheduled;
|
||||
unsigned Height;
|
||||
|
||||
SIBlockSchedCandidate()
|
||||
: Block(nullptr) {}
|
||||
SIBlockSchedCandidate() = default;
|
||||
|
||||
bool isValid() const { return Block; }
|
||||
|
||||
@ -409,9 +410,9 @@ class SIScheduler {
|
||||
SIScheduleBlockCreator BlockCreator;
|
||||
|
||||
public:
|
||||
SIScheduler(SIScheduleDAGMI *DAG) : DAG(DAG), BlockCreator(DAG) {};
|
||||
SIScheduler(SIScheduleDAGMI *DAG) : DAG(DAG), BlockCreator(DAG) {}
|
||||
|
||||
~SIScheduler() {};
|
||||
~SIScheduler() = default;
|
||||
|
||||
struct SIScheduleBlockResult
|
||||
scheduleVariant(SISchedulerBlockCreatorVariant BlockVariant,
|
||||
@ -445,13 +446,13 @@ public:
|
||||
}
|
||||
|
||||
MachineBasicBlock *getBB() { return BB; }
|
||||
MachineBasicBlock::iterator getCurrentTop() { return CurrentTop; };
|
||||
MachineBasicBlock::iterator getCurrentBottom() { return CurrentBottom; };
|
||||
MachineBasicBlock::iterator getCurrentTop() { return CurrentTop; }
|
||||
MachineBasicBlock::iterator getCurrentBottom() { return CurrentBottom; }
|
||||
LiveIntervals *getLIS() { return LIS; }
|
||||
MachineRegisterInfo *getMRI() { return &MRI; }
|
||||
const TargetRegisterInfo *getTRI() { return TRI; }
|
||||
SUnit& getEntrySU() { return EntrySU; };
|
||||
SUnit& getExitSU() { return ExitSU; };
|
||||
SUnit& getEntrySU() { return EntrySU; }
|
||||
SUnit& getExitSU() { return ExitSU; }
|
||||
|
||||
void restoreSULinksLeft();
|
||||
|
||||
@ -459,13 +460,14 @@ public:
|
||||
_Iterator End,
|
||||
unsigned &VgprUsage,
|
||||
unsigned &SgprUsage);
|
||||
|
||||
std::set<unsigned> getInRegs() {
|
||||
std::set<unsigned> InRegs;
|
||||
for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
|
||||
InRegs.insert(RegMaskPair.RegUnit);
|
||||
}
|
||||
return InRegs;
|
||||
};
|
||||
}
|
||||
|
||||
unsigned getVGPRSetID() const { return VGPRSetID; }
|
||||
unsigned getSGPRSetID() const { return SGPRSetID; }
|
||||
@ -486,6 +488,6 @@ public:
|
||||
std::vector<int> BottomUpIndex2SU;
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
} // end namespace llvm
|
||||
|
||||
#endif /* SIMACHINESCHEDULER_H_ */
|
||||
#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
|
||||
|
||||
@ -53,10 +53,28 @@
|
||||
#include "AMDGPUSubtarget.h"
|
||||
#include "SIInstrInfo.h"
|
||||
#include "SIMachineFunctionInfo.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/CodeGen/LiveInterval.h"
|
||||
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/SlotIndexes.h"
|
||||
#include "llvm/IR/CallingConv.h"
|
||||
#include "llvm/IR/DebugLoc.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include <cassert>
|
||||
#include <vector>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -71,9 +89,9 @@ enum {
|
||||
|
||||
struct PrintState {
|
||||
public:
|
||||
explicit PrintState(int State) : State(State) {}
|
||||
|
||||
int State;
|
||||
|
||||
explicit PrintState(int State) : State(State) {}
|
||||
};
|
||||
|
||||
static raw_ostream &operator<<(raw_ostream &OS, const PrintState &PS) {
|
||||
@ -103,7 +121,7 @@ struct WorkItem {
|
||||
MachineBasicBlock *MBB = nullptr;
|
||||
MachineInstr *MI = nullptr;
|
||||
|
||||
WorkItem() {}
|
||||
WorkItem() = default;
|
||||
WorkItem(MachineBasicBlock *MBB) : MBB(MBB) {}
|
||||
WorkItem(MachineInstr *MI) : MI(MI) {}
|
||||
};
|
||||
@ -162,7 +180,7 @@ public:
|
||||
}
|
||||
};
|
||||
|
||||
} // End anonymous namespace
|
||||
} // end anonymous namespace
|
||||
|
||||
char SIWholeQuadMode::ID = 0;
|
||||
|
||||
|
||||
@ -243,7 +243,7 @@ def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
|
||||
return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
|
||||
}]>;
|
||||
def vecspltisb : PatLeaf<(build_vector), [{
|
||||
return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
|
||||
return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr;
|
||||
}], VSPLTISB_get_imm>;
|
||||
|
||||
// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
|
||||
@ -251,7 +251,7 @@ def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
|
||||
return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
|
||||
}]>;
|
||||
def vecspltish : PatLeaf<(build_vector), [{
|
||||
return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
|
||||
return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr;
|
||||
}], VSPLTISH_get_imm>;
|
||||
|
||||
// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
|
||||
@ -259,7 +259,7 @@ def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
|
||||
return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
|
||||
}]>;
|
||||
def vecspltisw : PatLeaf<(build_vector), [{
|
||||
return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
|
||||
return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr;
|
||||
}], VSPLTISW_get_imm>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -20,31 +20,38 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#define DEBUG_TYPE "ppc-loop-preinc-prep"
|
||||
|
||||
#include "PPC.h"
|
||||
#include "PPCSubtarget.h"
|
||||
#include "PPCTargetMachine.h"
|
||||
#include "llvm/ADT/DepthFirstIterator.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/SmallSet.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/Analysis/CodeMetrics.h"
|
||||
#include "llvm/Analysis/InstructionSimplify.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/Analysis/LoopInfo.h"
|
||||
#include "llvm/Analysis/ScalarEvolution.h"
|
||||
#include "llvm/Analysis/ScalarEvolutionExpander.h"
|
||||
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
|
||||
#include "llvm/Analysis/ValueTracking.h"
|
||||
#include "llvm/IR/BasicBlock.h"
|
||||
#include "llvm/IR/CFG.h"
|
||||
#include "llvm/IR/Dominators.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/Instruction.h"
|
||||
#include "llvm/IR/Instructions.h"
|
||||
#include "llvm/IR/IntrinsicInst.h"
|
||||
#include "llvm/IR/Module.h"
|
||||
#include "llvm/IR/Value.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Transforms/Scalar.h"
|
||||
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
|
||||
#include "llvm/Transforms/Utils/Local.h"
|
||||
#include "llvm/Transforms/Utils/LoopUtils.h"
|
||||
#include "llvm/Transforms/Utils/ValueMapper.h"
|
||||
#include <cassert>
|
||||
#include <iterator>
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
// By default, we limit this to creating 16 PHIs (which is a little over half
|
||||
@ -54,14 +61,17 @@ static cl::opt<unsigned> MaxVars("ppc-preinc-prep-max-vars",
|
||||
cl::desc("Potential PHI threshold for PPC preinc loop prep"));
|
||||
|
||||
namespace llvm {
|
||||
|
||||
void initializePPCLoopPreIncPrepPass(PassRegistry&);
|
||||
}
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
namespace {
|
||||
|
||||
class PPCLoopPreIncPrep : public FunctionPass {
|
||||
public:
|
||||
static char ID; // Pass ID, replacement for typeid
|
||||
|
||||
PPCLoopPreIncPrep() : FunctionPass(ID), TM(nullptr) {
|
||||
initializePPCLoopPreIncPrepPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
@ -89,7 +99,8 @@ namespace {
|
||||
ScalarEvolution *SE;
|
||||
bool PreserveLCSSA;
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
char PPCLoopPreIncPrep::ID = 0;
|
||||
static const char *name = "Prepare loop for pre-inc. addressing modes";
|
||||
@ -103,6 +114,7 @@ FunctionPass *llvm::createPPCLoopPreIncPrepPass(PPCTargetMachine &TM) {
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
struct BucketElement {
|
||||
BucketElement(const SCEVConstant *O, Instruction *I) : Offset(O), Instr(I) {}
|
||||
BucketElement(Instruction *I) : Offset(nullptr), Instr(I) {}
|
||||
@ -118,7 +130,8 @@ namespace {
|
||||
const SCEV *BaseSCEV;
|
||||
SmallVector<BucketElement, 16> Elements;
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
static bool IsPtrInBounds(Value *BasePtr) {
|
||||
Value *StrippedBasePtr = BasePtr;
|
||||
@ -140,7 +153,7 @@ static Value *GetPointerOperand(Value *MemI) {
|
||||
return IMemI->getArgOperand(0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
bool PPCLoopPreIncPrep::runOnFunction(Function &F) {
|
||||
@ -394,7 +407,7 @@ bool PPCLoopPreIncPrep::runOnLoop(Loop *L) {
|
||||
Instruction *PtrIP = dyn_cast<Instruction>(Ptr);
|
||||
if (PtrIP && isa<Instruction>(NewBasePtr) &&
|
||||
cast<Instruction>(NewBasePtr)->getParent() == PtrIP->getParent())
|
||||
PtrIP = 0;
|
||||
PtrIP = nullptr;
|
||||
else if (isa<PHINode>(PtrIP))
|
||||
PtrIP = &*PtrIP->getParent()->getFirstInsertionPt();
|
||||
else if (!PtrIP)
|
||||
@ -437,4 +450,3 @@ bool PPCLoopPreIncPrep::runOnLoop(Loop *L) {
|
||||
|
||||
return MadeChange;
|
||||
}
|
||||
|
||||
|
||||
@ -14,7 +14,9 @@
|
||||
#include "CodeGenTarget.h"
|
||||
#include "CodeGenSchedule.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/StringExtras.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/MC/MCInstrItineraries.h"
|
||||
#include "llvm/MC/MCSchedule.h"
|
||||
#include "llvm/MC/SubtargetFeature.h"
|
||||
@ -27,6 +29,7 @@
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <iterator>
|
||||
#include <map>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
@ -42,7 +45,7 @@ class SubtargetEmitter {
|
||||
// The SchedClassDesc table indexes into a global write resource table, write
|
||||
// latency table, and read advance table.
|
||||
struct SchedClassTables {
|
||||
std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
|
||||
std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
|
||||
std::vector<MCWriteProcResEntry> WriteProcResources;
|
||||
std::vector<MCWriteLatencyEntry> WriteLatencies;
|
||||
std::vector<std::string> WriterNames;
|
||||
@ -81,10 +84,10 @@ class SubtargetEmitter {
|
||||
Record *ItinData,
|
||||
std::string &ItinString, unsigned NOperandCycles);
|
||||
void EmitStageAndOperandCycleData(raw_ostream &OS,
|
||||
std::vector<std::vector<InstrItinerary> >
|
||||
std::vector<std::vector<InstrItinerary>>
|
||||
&ProcItinLists);
|
||||
void EmitItineraries(raw_ostream &OS,
|
||||
std::vector<std::vector<InstrItinerary> >
|
||||
std::vector<std::vector<InstrItinerary>>
|
||||
&ProcItinLists);
|
||||
void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
|
||||
char Separator);
|
||||
@ -357,9 +360,8 @@ void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
|
||||
//
|
||||
void SubtargetEmitter::
|
||||
EmitStageAndOperandCycleData(raw_ostream &OS,
|
||||
std::vector<std::vector<InstrItinerary> >
|
||||
std::vector<std::vector<InstrItinerary>>
|
||||
&ProcItinLists) {
|
||||
|
||||
// Multiple processor models may share an itinerary record. Emit it once.
|
||||
SmallPtrSet<Record*, 8> ItinsDefSet;
|
||||
|
||||
@ -498,7 +500,7 @@ EmitStageAndOperandCycleData(raw_ostream &OS,
|
||||
int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
|
||||
InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
|
||||
FindOperandCycle,
|
||||
FindOperandCycle + NOperandCycles};
|
||||
FindOperandCycle + NOperandCycles };
|
||||
|
||||
// Inject - empty slots will be 0, 0
|
||||
ItinList[SchedClassIdx] = Intinerary;
|
||||
@ -530,13 +532,12 @@ EmitStageAndOperandCycleData(raw_ostream &OS,
|
||||
//
|
||||
void SubtargetEmitter::
|
||||
EmitItineraries(raw_ostream &OS,
|
||||
std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
|
||||
|
||||
std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
|
||||
// Multiple processor models may share an itinerary record. Emit it once.
|
||||
SmallPtrSet<Record*, 8> ItinsDefSet;
|
||||
|
||||
// For each processor's machine model
|
||||
std::vector<std::vector<InstrItinerary> >::iterator
|
||||
std::vector<std::vector<InstrItinerary>>::iterator
|
||||
ProcItinListsIter = ProcItinLists.begin();
|
||||
for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
|
||||
PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
|
||||
@ -1240,7 +1241,7 @@ void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
|
||||
<< "#endif\n";
|
||||
|
||||
if (SchedModels.hasItineraries()) {
|
||||
std::vector<std::vector<InstrItinerary> > ProcItinLists;
|
||||
std::vector<std::vector<InstrItinerary>> ProcItinLists;
|
||||
// Emit the stage data
|
||||
EmitStageAndOperandCycleData(OS, ProcItinLists);
|
||||
EmitItineraries(OS, ProcItinLists);
|
||||
@ -1424,13 +1425,13 @@ void SubtargetEmitter::run(raw_ostream &OS) {
|
||||
<< Target << "WriteProcResTable, "
|
||||
<< Target << "WriteLatencyTable, "
|
||||
<< Target << "ReadAdvanceTable, ";
|
||||
OS << '\n'; OS.indent(22);
|
||||
if (SchedModels.hasItineraries()) {
|
||||
OS << '\n'; OS.indent(22);
|
||||
OS << Target << "Stages, "
|
||||
<< Target << "OperandCycles, "
|
||||
<< Target << "ForwardingPaths";
|
||||
} else
|
||||
OS << "0, 0, 0";
|
||||
OS << "nullptr, nullptr, nullptr";
|
||||
OS << ");\n}\n\n";
|
||||
|
||||
OS << "} // end namespace llvm\n\n";
|
||||
@ -1510,7 +1511,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
|
||||
<< Target << "OperandCycles, "
|
||||
<< Target << "ForwardingPaths";
|
||||
} else
|
||||
OS << "0, 0, 0";
|
||||
OS << "nullptr, nullptr, nullptr";
|
||||
OS << ") {}\n\n";
|
||||
|
||||
EmitSchedModelHelpers(ClassName, OS);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user