RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-02-11 05:17:36 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Verify that explicit definitions in the TargetInstrDesc are matched by

Browse Source 
explicit register define operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71933 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2009-05-16 07:25:20 +00:00
parent d6fb97761e
commit 44b27e5c75
1 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/CodeGen/MachineVerifier.cpp
View File

@ -327,6 +327,18 @@ void
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
{ {
const MachineInstr *MI = MO->getParent(); const MachineInstr *MI = MO->getParent();
const TargetInstrDesc &TI = MI->getDesc();
// The first TI.NumDefs operands must be explicit register defines
if (MONum < TI.getNumDefs()) {
if (!MO->isReg())
report("Explicit definition must be a register", MO, MONum);
else if (!MO->isDef())
report("Explicit definition marked as use", MO, MONum);
else if (MO->isImplicit())
report("Explicit definition marked as implicit", MO, MONum);
}
switch (MO->getType()) { switch (MO->getType()) {
case MachineOperand::MO_Register: { case MachineOperand::MO_Register: {
const unsigned Reg = MO->getReg(); const unsigned Reg = MO->getReg();
@ -374,7 +386,6 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
} }
// Check register classes. // Check register classes.
const TargetInstrDesc &TI = MI->getDesc();
if (MONum < TI.getNumOperands() && !MO->isImplicit()) { if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
const TargetOperandInfo &TOI = TI.OpInfo[MONum]; const TargetOperandInfo &TOI = TI.OpInfo[MONum];
unsigned SubIdx = MO->getSubReg(); unsigned SubIdx = MO->getSubReg();