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AMDGPU: Prune includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278391 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11,22 +11,16 @@
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AMDGPUInstrPrinter;
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class AMDGPUSubtarget;
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class AMDGPUTargetMachine;
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class FunctionPass;
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class GCNTargetMachine;
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struct MachineSchedContext;
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class MCAsmInfo;
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class raw_ostream;
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class ScheduleDAGInstrs;
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class ModulePass;
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class Pass;
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class Target;
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class TargetMachine;
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class PassRegistry;
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// R600 Passes
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FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
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@ -48,13 +42,10 @@ FunctionPass *createSIWholeQuadModePass();
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FunctionPass *createSILowerControlFlowPass();
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FunctionPass *createSIFixControlFlowLiveIntervalsPass();
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FunctionPass *createSIFixSGPRCopiesPass();
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FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
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FunctionPass *createSIDebuggerInsertNopsPass();
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FunctionPass *createSIInsertWaitsPass();
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FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
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ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C);
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ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
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void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
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extern char &AMDGPUAnnotateKernelFeaturesID;
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@ -86,7 +77,6 @@ FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
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void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
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extern char &AMDGPUPromoteAllocaID;
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FunctionPass *createAMDGPUAddDivergenceMetadata(const AMDGPUSubtarget &ST);
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Pass *createAMDGPUStructurizeCFGPass();
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FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
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ModulePass *createAMDGPUAlwaysInlinePass();
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@ -13,6 +13,7 @@
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Module.h"
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@ -23,19 +23,11 @@
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#include "R600MachineScheduler.h"
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "llvm/Analysis/Passes.h"
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#include "SIMachineScheduler.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Verifier.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_os_ostream.h"
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#include "llvm/Transforms/IPO.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/Scalar/GVN.h"
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@ -99,6 +91,10 @@ static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
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return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
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}
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static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
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return new SIScheduleDAGMI(C);
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}
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static MachineSchedRegistry
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R600SchedRegistry("r600", "Run R600's custom scheduler",
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createR600MachineScheduler);
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@ -19,7 +19,6 @@
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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class StringRef;
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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@ -28,10 +27,10 @@ class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCTargetOptions;
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class StringRef;
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class Target;
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class Triple;
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class raw_pwrite_stream;
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class raw_ostream;
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extern Target TheAMDGPUTarget;
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extern Target TheGCNTarget;
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@ -1665,10 +1665,6 @@ SIScheduleDAGMI::SIScheduleDAGMI(MachineSchedContext *C) :
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SIScheduleDAGMI::~SIScheduleDAGMI() {
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}
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ScheduleDAGInstrs *llvm::createSIMachineScheduler(MachineSchedContext *C) {
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return new SIScheduleDAGMI(C);
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}
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// Code adapted from scheduleDAG.cpp
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// Does a topological sort over the SUs.
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// Both TopDown and BottomUp
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