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[Hexagon] Standardize pseudo-instructions for calls and returns

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- CALLv3nr        PS_call_nr
- CALLRv3nr       PS_callr_nr
- CALLstk         PS_call_stk

- TCRETURNi       PS_tailcall_i
- TCRETURNr       PS_tailcall_r

- JMPret          PS_jmpret
- JMPrett         PS_jmprett
- JMPretf         PS_jmpretf
- JMPrettnew      PS_jmprettnew
- JMPretfnew      PS_jmpretfnew
- JMPrettnewpt    PS_jmprettnewpt
- JMPretfnewpt    PS_jmpretfnewpt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278499 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-08-12 11:12:02 +00:00
parent a8e8317d69
commit 4502b2e1ab
7 changed files with 63 additions and 61 deletions
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10
lib/Target/Hexagon/HexagonFrameLowering.cpp
View File

@ -291,7 +291,7 @@ namespace {
bool hasTailCall(const MachineBasicBlock &MBB) {
MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
unsigned RetOpc = I->getOpcode();
return RetOpc == Hexagon::TCRETURNi || RetOpc == Hexagon::TCRETURNr;
return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
}
/// Returns true if MBB contains an instruction that returns.
@ -584,7 +584,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
// registers inline (i.e. did not use a spill function), then call
// the stack checker directly.
if (EnableStackOVFSanitizer && !PrologueStubs)
BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::CALLstk))
BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
.addExternalSymbol("__runtime_stack_check");
}
@ -646,16 +646,16 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
COpc == Hexagon::CALLv3nr || COpc == Hexagon::CALLRv3nr)
COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
NeedsDeallocframe = false;
}
if (!NeedsDeallocframe)
return;
// If the returning instruction is JMPret, replace it with dealloc_return,
// If the returning instruction is PS_jmpret, replace it with dealloc_return,
// otherwise just add deallocframe. The function could be returning via a
// tail call.
if (RetOpc != Hexagon::JMPret || DisableDeallocRet) {
if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::L2_deallocframe));
return;
}

10
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -891,7 +891,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
}
unsigned OpCode = DoesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3;
unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
Glue = Chain.getValue(1);
@ -1567,10 +1567,10 @@ HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
if (InFlag) {
SDValue Ops[] = { Chain, TGA,
DAG.getRegister(Hexagon::R0, PtrVT), *InFlag };
Chain = DAG.getNode(HexagonISD::CALLv3, dl, NodeTys, Ops);
Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
} else {
SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT)};
Chain = DAG.getNode(HexagonISD::CALLv3, dl, NodeTys, Ops);
Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
}
// Inform MFI that function has calls.
@ -2218,9 +2218,9 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
case HexagonISD::CALL: return "HexagonISD::CALL";
case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
case HexagonISD::CALLR: return "HexagonISD::CALLR";
case HexagonISD::CALLv3nr: return "HexagonISD::CALLv3nr";
case HexagonISD::CALLv3: return "HexagonISD::CALLv3";
case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
case HexagonISD::CONST32: return "HexagonISD::CONST32";

4
lib/Target/Hexagon/HexagonISelLowering.h
View File

@ -36,8 +36,8 @@ bool isPositiveHalfWord(SDNode *N);
AT_GOT, // Index in GOT.
AT_PCREL, // Offset relative to PC.
CALLv3, // A V3+ call instruction.
CALLv3nr, // A V3+ call instruction that doesn't return.
CALL, // Function call.
CALLnr, // Function call that does not return.
CALLR,
RET_FLAG, // Return with a flag operand.

22
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1297,10 +1297,10 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MBB.erase(MI);
return true;
}
case Hexagon::TCRETURNi:
case Hexagon::PS_tailcall_i:
MI.setDesc(get(Hexagon::J2_jump));
return true;
case Hexagon::TCRETURNr:
case Hexagon::PS_tailcall_r:
MI.setDesc(get(Hexagon::J2_jumpr));
return true;
}
@ -2175,7 +2175,7 @@ bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
return false;
case Hexagon::J2_jump: // bits<24> dst; // r22:2
case Hexagon::J2_call:
case Hexagon::CALLv3nr:
case Hexagon::PS_call_nr:
return isInt<24>(offset);
case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
case Hexagon::J2_jumpf:
@ -2973,7 +2973,7 @@ bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
unsigned Opc = CallMI.getOpcode();
return Opc == Hexagon::CALLv3nr || Opc == Hexagon::CALLRv3nr;
return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
}
@ -3714,19 +3714,19 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
case Hexagon::L2_deallocframe:
return HexagonII::HSIG_L2;
case Hexagon::EH_RETURN_JMPR:
case Hexagon::JMPret :
case Hexagon::PS_jmpret:
// jumpr r31
// Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
DstReg = MI.getOperand(0).getReg();
if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
return HexagonII::HSIG_L2;
break;
case Hexagon::JMPrett:
case Hexagon::JMPretf:
case Hexagon::JMPrettnewpt:
case Hexagon::JMPretfnewpt :
case Hexagon::JMPrettnew :
case Hexagon::JMPretfnew :
case Hexagon::PS_jmprett:
case Hexagon::PS_jmpretf:
case Hexagon::PS_jmprettnewpt:
case Hexagon::PS_jmpretfnewpt:
case Hexagon::PS_jmprettnew:
case Hexagon::PS_jmpretfnew:
DstReg = MI.getOperand(1).getReg();
SrcReg = MI.getOperand(0).getReg();
// [if ([!]p0[.new])] jumpr r31

16
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -1588,7 +1588,7 @@ let isTerminator = 1, hasSideEffects = 0 in {
defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
let isReturn = 1, isCodeGenOnly = 1 in
defm JMPret : JMPR_base<"JMPret">, PredNewRel;
defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel;
}
let validSubTargets = HasV60SubT in
@ -1613,7 +1613,7 @@ defm J2_jump : JMPpt_base<"JMP">;
def: Pat<(br bb:$dst),
(J2_jump brtarget:$dst)>;
def: Pat<(retflag),
(JMPret (i32 R31))>;
(PS_jmpret (i32 R31))>;
def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
(J2_jumpt PredRegs:$src1, bb:$offset)>;
@ -4821,20 +4821,20 @@ def J2_callr : JUMPR_MISC_CALLR<0, 1>;
// Indirect tail-call.
let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
isTerminator = 1, isCodeGenOnly = 1 in
def TCRETURNr : T_JMPr;
def PS_tailcall_r : T_JMPr;
// Direct tail-calls.
let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
isTerminator = 1, isCodeGenOnly = 1 in
def TCRETURNi : JInst<(outs), (ins calltarget:$dst), "", []>;
def PS_tailcall_i : JInst<(outs), (ins calltarget:$dst), "", []>;
//Tail calls.
def: Pat<(HexagonTCRet tglobaladdr:$dst),
(TCRETURNi tglobaladdr:$dst)>;
(PS_tailcall_i tglobaladdr:$dst)>;
def: Pat<(HexagonTCRet texternalsym:$dst),
(TCRETURNi texternalsym:$dst)>;
def: Pat<(HexagonTCRet (i32 IntRegs:$dst)),
(TCRETURNr IntRegs:$dst)>;
(PS_tailcall_i texternalsym:$dst)>;
def: Pat<(HexagonTCRet I32:$dst),
(PS_tailcall_r I32:$dst)>;
// Map from r0 = and(r1, 65535) to r0 = zxth(r1)
def: Pat<(and (i32 IntRegs:$src1), 65535),

34
lib/Target/Hexagon/HexagonInstrInfoV3.td
View File

@ -11,10 +11,10 @@
//
//===----------------------------------------------------------------------===//
def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
def callv3 : SDNode<"HexagonISD::CALL", SDT_SPCall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
def callv3nr : SDNode<"HexagonISD::CALLnr", SDT_SPCall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
//===----------------------------------------------------------------------===//
@ -66,11 +66,13 @@ multiclass T_Calls<bit CSR, string ExtStr> {
defm J2_call: T_Calls<1, "">, PredRel;
let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
def CALLv3nr : T_Call<1, "">, PredRel;
let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
Defs = VolatileV3.Regs in
def PS_call_nr : T_Call<1, "">, PredRel;
let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [PC, R31, R6, R7, P0] in
def CALLstk : T_Call<0, "">, PredRel;
let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
Defs = [PC, R31, R6, R7, P0] in
def PS_call_stk : T_Call<0, "">, PredRel;
//===----------------------------------------------------------------------===//
// J -
@ -83,7 +85,7 @@ def CALLstk : T_Call<0, "">, PredRel;
// Call subroutine from register.
let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
def CALLRv3nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
}
//===----------------------------------------------------------------------===//
@ -175,21 +177,21 @@ let AddedComplexity = 200 in {
// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
// Map call instruction
def : Pat<(callv3 (i32 IntRegs:$dst)),
(J2_callr (i32 IntRegs:$dst))>;
def : Pat<(callv3 I32:$dst),
(J2_callr I32:$dst)>;
def : Pat<(callv3 tglobaladdr:$dst),
(J2_call tglobaladdr:$dst)>;
(J2_call tglobaladdr:$dst)>;
def : Pat<(callv3 texternalsym:$dst),
(J2_call texternalsym:$dst)>;
(J2_call texternalsym:$dst)>;
def : Pat<(callv3 tglobaltlsaddr:$dst),
(J2_call tglobaltlsaddr:$dst)>;
(J2_call tglobaltlsaddr:$dst)>;
def : Pat<(callv3nr (i32 IntRegs:$dst)),
(CALLRv3nr (i32 IntRegs:$dst))>;
def : Pat<(callv3nr I32:$dst),
(PS_callr_nr I32:$dst)>;
def : Pat<(callv3nr tglobaladdr:$dst),
(CALLv3nr tglobaladdr:$dst)>;
(PS_call_nr tglobaladdr:$dst)>;
def : Pat<(callv3nr texternalsym:$dst),
(CALLv3nr texternalsym:$dst)>;
(PS_call_nr texternalsym:$dst)>;
//===----------------------------------------------------------------------===//
// :raw form of vrcmpys:hi/lo insns

28
lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
View File

@ -262,7 +262,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
case Hexagon::JMPret:
case Hexagon::PS_jmpret:
// jumpr r31
// Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
DstReg = MCI.getOperand(0).getReg();
@ -275,12 +275,12 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
case Hexagon::J2_jumprf:
case Hexagon::J2_jumprtnew:
case Hexagon::J2_jumprfnew:
case Hexagon::JMPrett:
case Hexagon::JMPretf:
case Hexagon::JMPrettnew:
case Hexagon::JMPretfnew:
case Hexagon::JMPrettnewpt:
case Hexagon::JMPretfnewpt:
case Hexagon::PS_jmprett:
case Hexagon::PS_jmpretf:
case Hexagon::PS_jmprettnew:
case Hexagon::PS_jmpretfnew:
case Hexagon::PS_jmprettnewpt:
case Hexagon::PS_jmpretfnewpt:
DstReg = MCI.getOperand(1).getReg();
SrcReg = MCI.getOperand(0).getReg();
// [if ([!]p0[.new])] jumpr r31
@ -811,25 +811,25 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
break; // none SUBInst deallocframe
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
case Hexagon::JMPret:
case Hexagon::PS_jmpret:
Result.setOpcode(Hexagon::V4_SL2_jumpr31);
break; // none SUBInst jumpr r31
case Hexagon::J2_jumprf:
case Hexagon::JMPretf:
case Hexagon::PS_jmpretf:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_f);
break; // none SUBInst if (!p0) jumpr r31
case Hexagon::J2_jumprfnew:
case Hexagon::JMPretfnewpt:
case Hexagon::JMPretfnew:
case Hexagon::PS_jmpretfnewpt:
case Hexagon::PS_jmpretfnew:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_fnew);
break; // none SUBInst if (!p0.new) jumpr:nt r31
case Hexagon::J2_jumprt:
case Hexagon::JMPrett:
case Hexagon::PS_jmprett:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_t);
break; // none SUBInst if (p0) jumpr r31
case Hexagon::J2_jumprtnew:
case Hexagon::JMPrettnewpt:
case Hexagon::JMPrettnew:
case Hexagon::PS_jmprettnewpt:
case Hexagon::PS_jmprettnew:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_tnew);
break; // none SUBInst if (p0.new) jumpr:nt r31
case Hexagon::L2_loadrb_io: